SLAZ090Y October   2012  – May 2021 CC430F5123

 

  1.   1
  2.   2
  3.   3
  4.   4
  5.   5
    1.     6
    2.     7
      1.      8
    3.     9
  6.   10
    1.     11
    2.     12
    3.     13
    4.     14
    5.     15
    6.     16
    7.     17
    8.     18
    9.     19
    10.     20
    11.     21
    12.     22
    13.     23
    14.     24
    15.     25
    16.     26
    17.     27
    18.     28
    19.     29
    20.     30
    21.     31
    22.     32
    23.     33
    24.     34
    25.     35
    26.     36
    27.     37
    28.     38
    29.     39
    30.     40
    31.     41
    32.     42
    33.     43
    34.     44
    35.     45
    36.     46
    37.     47
    38.     48
    39.     49
    40.     50
    41.     51
    42.     52
    43.     53
    44.     54
    45.     55
    46.     56
  7.   57

6.33 RF1A2

RF1A Module

Category

Functional

Function

RXFIFO overflow flag does not work as intended

Description

In addition to having a 64-byte long RX FIFO, the CC430 has a one byte long pre-fetch buffer between the FIFO and the RF1A module. It also has buffers for status registers and CRC bytes. If more than 65 bytes have been received (the FIFO and the pre-fetch buffer are full) without reading the RX FIFO, the radio will enter RXFIFO_OVERFLOW state. There are, however, some cases where the radio will be stuck in RX state instead of entering RXFIFO_OVERFLOW state. Below is a table showing the register settings that will cause this problem. APPEND_STATUS is found in the PKTCTRL1 register, and CRC_EN is found in the PKTCTRL0 register.

Setting IOCFGx=0x06 should mean that the GDO signal is deasserted when the RXFIFO overflows. In the cases where the radio is stuck in RX state, the GDOx pin will not be deasserted.

When the radio is stuck in this RX state it draws current as if it was in the RX state, but it will not be able to receive any more data. The only way to get out of this state is to issue an SIDLE strobe and then flush the FIFO (SFRX).

Workaround

In applications where the packets are short enough to fit in the RX FIFO and one wants to wait for the whole packet to be received before starting to read the RX FIFO, for variable packet length mode (PKTCTRL0.LENGTH_CONFIG=1) the PKTLEN register should be set to 61 to make sure the whole packet including status bytes are 64 bytes or less (length byte (61) + 61 payload bytes + 2 status bytes = 64 bytes) or PKTLEN = 62 if fixed packet length mode is used (PKTCTRL0.LENGTH_CONFIG=0). In application where the packets do not fit in the RX FIFO, one must start reading the RX FIFO before it reaches its limit (64 bytes).