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  • MSP430FR604x(1), MSP430FR603x(1) Ultrasonic Sensing MSP430™ Microcontrollers for Water‑Metering Applications

    • SLASEB7D June   2017  – December 2020

      PRODUCTION DATA  

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  • MSP430FR604x(1), MSP430FR603x(1) Ultrasonic Sensing MSP430™ Microcontrollers for Water‑Metering Applications
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagrams
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Buffer Type
    6. 7.6 Connection of Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Typical Characteristics, Active Mode Supply Currents
    6. 8.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 8.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 8.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 8.9  Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
    10. 8.10 Typical Characteristics, Low-Power Mode Supply Currents
    11. 8.11 Typical Characteristics, Current Consumption per Module (1)
    12. 8.12 Thermal Resistance Characteristics for 100-Pin LQFP (PZ) Package
    13. 8.13 Timing and Switching Characteristics
      1. 8.13.1  Power Supply Sequencing
        1. 8.13.1.1 Brownout and Device Reset Power Ramp Requirements
        2. 8.13.1.2 SVS
      2. 8.13.2  Reset Timing
        1. 8.13.2.1 Reset Input
      3. 8.13.3  Clock Specifications
        1. 8.13.3.1 Low-Frequency Crystal Oscillator, LFXT
        2. 8.13.3.2 High-Frequency Crystal Oscillator, HFXT
        3. 8.13.3.3 DCO
        4. 8.13.3.4 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. 8.13.3.5 Module Oscillator (MODOSC)
      4. 8.13.4  Wake-up Characteristics
        1. 8.13.4.1 Wake-up Times From Low-Power Modes and Reset
        2. 8.13.4.2 Typical Wake-up Charges
        3. 8.13.4.3 Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 8.13.5  Digital I/Os
        1. 8.13.5.1 Digital Inputs
        2. 8.13.5.2 Digital Outputs
        3. 8.13.5.3 Typical Characteristics, Digital Outputs
      6. 8.13.6  LEA
        1. 8.13.6.1 Low-Energy Accelerator (LEA) Performance
      7. 8.13.7  Timer_A and Timer_B
        1. 8.13.7.1 Timer_A
        2. 8.13.7.2 Timer_B
      8. 8.13.8  eUSCI
        1. 8.13.8.1 eUSCI (UART Mode) Clock Frequency
        2. 8.13.8.2 eUSCI (UART Mode) Switching Characteristics
        3. 8.13.8.3 eUSCI (SPI Master Mode) Clock Frequency
        4. 8.13.8.4 eUSCI (SPI Master Mode) Switching Characteristics
        5. 8.13.8.5 eUSCI (SPI Master Mode) Timing Diagrams
        6. 8.13.8.6 eUSCI (SPI Slave Mode) Switching Characteristics
        7. 8.13.8.7 eUSCI (SPI Slave Mode) Timing Diagrams
        8. 8.13.8.8 eUSCI (I2C Mode) Switching Characteristics
        9. 8.13.8.9 eUSCI (SPI Slave Mode) Timing Diagrams
      9. 8.13.9  Segment LCD Controller
        1. 8.13.9.1 LCD_C Recommended Operating Conditions
        2. 8.13.9.2 LCD_C Electrical Characteristics
      10. 8.13.10 ADC12_B
        1. 8.13.10.1 12-Bit ADC, Power Supply and Input Range Conditions
        2. 8.13.10.2 12-Bit ADC, Timing Parameters
        3. 8.13.10.3 12-Bit ADC, Linearity Parameters
        4. 8.13.10.4 12-Bit ADC, Dynamic Performance With External Reference
        5. 8.13.10.5 12-Bit ADC, Dynamic Performance With Internal Reference
        6. 8.13.10.6 12-Bit ADC, Temperature Sensor and Built-In V1/2
        7. 8.13.10.7 12-Bit ADC, External Reference
        8. 8.13.10.8 Temperature Sensor Typical Characteristics
      11. 8.13.11 Reference
        1. 8.13.11.1 REF, Built-In Reference
      12. 8.13.12 Comparator
        1. 8.13.12.1 Comparator_E
      13. 8.13.13 FRAM
        1. 8.13.13.1 FRAM
      14. 8.13.14 USS
        1. 8.13.14.1 USS Recommended Operating Conditions
        2. 8.13.14.2 USS LDO
        3. 8.13.14.3 USSXTAL
        4. 8.13.14.4 USS HSPLL
        5. 8.13.14.5 USS SDHS
        6. 8.13.14.6 USS PHY Output Stage
        7. 8.13.14.7 USS PHY Input Stage, Multiplexer
        8. 8.13.14.8 USS PGA
        9. 8.13.14.9 USS Bias Voltage Generator
      15. 8.13.15 Emulation and Debug
        1. 8.13.15.1 JTAG and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Ultrasonic Sensing Solution (USS) Module
    4. 9.4  Low-Energy Accelerator (LEA) for Signal Processing
    5. 9.5  Operating Modes
      1. 9.5.1 Peripherals in Low-Power Modes
      2. 9.5.2 Idle Currents of Peripherals in LPM3 and LPM4
    6. 9.6  Interrupt Vector Table and Signatures
    7. 9.7  Bootloader (BSL)
    8. 9.8  JTAG Operation
      1. 9.8.1 JTAG Standard Interface
      2. 9.8.2 Spy-Bi-Wire (SBW) Interface
    9. 9.9  FRAM Controller A (FRCTL_A)
    10. 9.10 RAM
    11. 9.11 Tiny RAM
    12. 9.12 Memory Protection Unit (MPU) Including IP Encapsulation
    13. 9.13 Peripherals
      1. 9.13.1  Digital I/O
      2. 9.13.2  Oscillator and Clock System (CS)
      3. 9.13.3  Power-Management Module (PMM)
      4. 9.13.4  Hardware Multiplier (MPY)
      5. 9.13.5  Real-Time Clock (RTC_C)
      6. 9.13.6  Measurement Test Interface (MTIF)
      7. 9.13.7  Watchdog Timer (WDT_A)
      8. 9.13.8  System Module (SYS)
      9. 9.13.9  DMA Controller
      10. 9.13.10 Enhanced Universal Serial Communication Interface (eUSCI)
      11. 9.13.11 TA0, TA1, and TA4
      12. 9.13.12 TA2 and TA3
      13. 9.13.13 TB0
      14. 9.13.14 ADC12_B
      15. 9.13.15 USS
      16. 9.13.16 Comparator_E
      17. 9.13.17 CRC16
      18. 9.13.18 CRC32
      19. 9.13.19 AES256 Accelerator
      20. 9.13.20 True Random Seed
      21. 9.13.21 Shared Reference (REF)
      22. 9.13.22 LCD_C
      23. 9.13.23 Embedded Emulation
        1. 9.13.23.1 Embedded Emulation Module (EEM) (S Version)
        2. 9.13.23.2 EnergyTrace++ Technology
    14. 9.14 Input/Output Diagrams
      1. 9.14.1  Port Function Select Registers (PySEL1 , PySEL0)
      2. 9.14.2  Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
      3. 9.14.3  Port P1 (P1.2 to P1.7) Input/Output With Schmitt Trigger
      4. 9.14.4  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
      5. 9.14.5  Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
      6. 9.14.6  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      7. 9.14.7  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      8. 9.14.8  Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      9. 9.14.9  Port P6 (P6.0) Input/Output With Schmitt Trigger
      10. 9.14.10 Port P6 (P6.1 to P6.5) Input/Output With Schmitt Trigger
      11. 9.14.11 Port P6 (P6.6 and P6.7) Input/Output With Schmitt Trigger
      12. 9.14.12 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
      13. 9.14.13 Port P7 (P7.4) Input/Output With Schmitt Trigger
      14. 9.14.14 Port P7 (P7.5) Input/Output With Schmitt Trigger
      15. 9.14.15 Port P7 (P7.6 and P7.7) Input/Output With Schmitt Trigger
      16. 9.14.16 Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
      17. 9.14.17 Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger
      18. 9.14.18 Port P9 (P9.0 to P9.3) Input/Output With Schmitt Trigger
      19. 9.14.19 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
      20. 9.14.20 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
      21. 9.14.21 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
    15. 9.15 Device Descriptors (TLV)
    16. 9.16 Memory Map
      1. 9.16.1 Peripheral File Map
    17. 9.17 Identification
      1. 9.17.1 Revision Identification
      2. 9.17.2 Device Identification
      3. 9.17.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1  Power Supply Decoupling and Bulk Capacitors
      2. 10.1.2  External Oscillator (HFXT and LFXT)
      3. 10.1.3  USS Oscillator (USSXT)
      4. 10.1.4  Transducer Connection to the USS Module
      5. 10.1.5  Charge Pump Control of Input Multiplexer
      6. 10.1.6  JTAG
      7. 10.1.7  Reset
      8. 10.1.8  Unused Pins
      9. 10.1.9  General Layout Recommendations
      10. 10.1.10 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 ADC12_B Peripheral
        1. 10.2.1.1 Partial Schematic
        2. 10.2.1.2 Design Requirements
        3. 10.2.1.3 Detailed Design Procedure
        4. 10.2.1.4 Layout Guidelines
      2. 10.2.2 LCD_C Peripheral
        1. 10.2.2.1 Partial Schematic
        2. 10.2.2.2 Design Requirements
        3. 10.2.2.3 Detailed Design Procedure
        4. 10.2.2.4 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Getting Started
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 Support Resources
    6. 11.6 Export Control Notice
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
    9. 11.9 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE
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DATA SHEET

MSP430FR604x(1), MSP430FR603x(1) Ultrasonic Sensing MSP430™ Microcontrollers for Water‑Metering Applications

1 Features

  • Best-in-class ultrasonic water-flow measurement with ultra-low power consumption
    • <25-ps differential time-of-flight (dTOF) accuracy
    • High-precision time measurement resolution of <5 ps
    • Ability to detect low flow rates (<1 liter per hour)
    • Approximately 3-µA overall current consumption with one measurement per second
  • Compliant to and exceeds ISO 4064, OIML R49, and EN 1434 accuracy standards
  • Ability to directly interface standard ultrasonic sensors (up to 2.5 MHz)
  • Integrated analog front end – ultrasonic sensing solution (USS)
    • Programmable pulse generation (PPG) to generate pulses at different frequencies
    • Integrated physical interface (PHY) with low-impedance (4-Ω) output driver to control input and output channels
    • High-performance high-speed 12-bit sigma-delta ADC (SDHS) with output data rates up to 8 Msps
    • Programmable gain amplifier (PGA) with –6.5 dB to 30.8 dB
    • High-performance phase-locked loop (PLL) with output range of 68 MHz to 80 MHz
  • Metering test interface (MTIF)
    • Pulse generator and pulse counter
    • Pulse rates up to 1016 pulses per second (p/s)
    • Count capacity up to 65535 (16 bits)
    • Operates in LPM3.5 with 200 nA (typical)
  • Low-energy accelerator (LEA)
    • Operation independent of CPU
    • 4KB of RAM shared with CPU
    • Efficient 256-point complex FFT:
      Up to 40× faster than Arm®Cortex®-M0+ core
  • Embedded microcontroller
    • 16-bit RISC architecture up to 16‑MHz clock
    • Wide supply voltage range from 3.6 V down to 1.8 V (minimum supply voltage is restricted by SVS levels, see the SVS specifications)
  • Optimized ultra-low-power modes
    • Active mode: approximately 120 µA/MHz
    • Standby mode with real-time clock (RTC) (LPM3.5): 450 nA
    • Shutdown (LPM4.5): 30 nA
  • Ferroelectric random access memory (FRAM)
    • Up to 256KB of nonvolatile memory
    • Ultra-low-power writes
    • Fast write at 125 ns per word (64KB in 4 ms)
    • Unified memory = program + data + storage in one space
    • 1015 write cycle endurance
    • Radiation resistant and nonmagnetic
  • Intelligent digital peripherals
    • 32-bit hardware multiplier (MPY)
    • 6-channel internal DMA
    • RTC with calendar and alarm functions
    • Six 16-bit timers with up to seven capture/compare registers each
    • 32-bit and 16-bit cyclic redundancy check (CRC)
  • High-performance analog
    • 16-channel analog comparator
    • 12-bit SAR ADC featuring window comparator, internal reference, and sample-and-hold, up to 16 external input channels
    • Integrated LCD driver with contrast control for up to 264 segments
  • Multifunction input/output ports
    • Accessible bit-, byte-, and word-wise (in pairs)
    • Edge-selectable wake from LPM on all ports
    • Programmable pullup and pulldown on all ports
  • Code security and encryption
    • 128- or 256-bit AES security encryption and decryption coprocessor
    • Random number seed for random number generation algorithms
    • IP encapsulation protects memory from external access
    • FRAM provides inherent security advantages
  • Enhanced serial communication
    • Up to four eUSCI_A serial communication ports
      • UART with automatic baud-rate detection
      • IrDA encode and decode
    • Up to two eUSCI_B serial communication ports
      • I2C with multiple-slave addressing
    • Hardware UART or I2C bootloader (BSL)
  • Flexible clock system
    • Fixed-frequency DCO with 10 selectable factory-trimmed frequencies
    • Low-power low-frequency internal clock source (VLO)
    • 32-kHz crystals (LFXT)
    • High-frequency crystals (HFXT)
  • Development tools and software (also see Tools and Software)
    • Ultrasonic Sensing Design Center graphical user interface
    • Ultrasonic sensing software library
    • EVM430-FR6047 water meter evaluation module
    • MSP-TS430PZ100E target socket board for 100-pin package
    • Free professional development environments with EnergyTrace++ technology
    • MSP430Ware™ for MSP430™ microcontrollers
  • Device Comparison summarizes the available device variants and package options
SLASEB77493. The RTC is clocked by a 3.7-pF crystal.

2 Applications

  • Ultrasonic smart water meter
  • Ultrasonic smart heat meter
  • Liquid level sensing
  • Water leak detector

3 Description

The Texas Instruments MSP430FR604x and MSP430FR603x family of ultrasonic sensing and measurement SoCs are powerful, highly integrated microcontrollers (MCUs) that are optimized for water and heat meters. The MSP430FR604x MCUs offer an integrated ultrasonic sensing solution (USS) module, which provides high accuracy for a wide range of flow rates. The USS module helps achieve ultra-low-power metering combined with lower system cost due to maximum integration requiring very few external components. MSP430FR604x and MSP430FR603x MCUs implement a high-speed ADC-based signal acquisition followed by optimized digital signal processing using the integrated low-energy accelerator (LEA) module to deliver a high-accuracy metering solution with ultra-low power optimum for battery-powered metering applications.

The USS module includes a programmable pulse generator (PPG) and a physical interface (PHY) with a low-impedance output driver for optimum sensor excitation and accurate impendence matching to deliver best results for zero-flow drift (ZFD). The module also includes a programmable gain amplifier (PGA) and a high-speed 12-bit 8-Msps sigma-delta ADC (SDHS) for accurate signal acquisition from industry-standard ultrasonic transducers.

Additionally, MSP430FR604x and MSP430FR603x MCUs integrate other peripherals to improve system integration for metering. The devices have a metering test interface (MTIF) module to implement pulse generation to indicate flow measured by the meter. The MSP430FR604x and MSP430FR603x MCUs also have an on-chip 8-mux LCD driver, an RTC, a 12-bit SAR ADC, an analog comparator, an advanced encryption accelerator (AES256), and a cyclic redundancy check (CRC) module.

MSP430FR604x and MSP430FR603x MCUs are supported by an extensive hardware and software ecosystem with reference designs and code examples to get your design started quickly. Development kits include the MSP‑TS430PZ100E 100-pin target development board and EVM430‑FR6047 ultrasonic water flow meter EVM. TI also provides free software including the ultrasonic sensing design center, ultrasonic sensing software library, and MSP430Ware™ software.

TI's MSP430 ultra-low-power (ULP) FRAM microcontroller platform combines uniquely embedded FRAM and a holistic ultra-low-power system architecture, letting system designers increase performance while lowering energy consumption. FRAM technology combines the low-energy fast writes, flexibility, and endurance of RAM with the nonvolatility of flash.

For complete module descriptions, see the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide.

Device Information(1)(2)
PART NUMBER PACKAGE BODY SIZE(3)
MSP430FR6047IPZ
MSP430FR60471IPZ
MSP430FR6045IPZ
MSP430FR6037IPZ
MSP430FR60371IPZ
MSP430FR6035IPZ		 LQFP (100) 14 mm × 14 mm
(1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 12, or see the TI website at www.ti.com.
(2) For a comparison of all available device variants, see Section 6.
(3) The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 12.

4 Functional Block Diagrams

Figure 4-1 and Figure 4-2 show the functional block diagrams of the devices.

GUID-B12533C9-F42B-48BA-BBD3-0C35936688A1-low.gif
The device has 8KB of RAM, and 4KB of the RAM is shared with the LEA subsystem.
Figure 4-1 MSP430FR604x Functional Block Diagram
GUID-2A86FA6A-BD94-435B-868F-7DB03FC58BBB-low.gif
The device has 8KB of RAM, and 4KB of the RAM is shared with the LEA subsystem.
Figure 4-2 MSP430FR603x Functional Block Diagram

5 Revision History

Changes from revision C to revision D

Changes from September 26, 2018 to December 1, 2020

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Changed Section 6.1, Related Products Go
  • Added the note that begins "XT1CLK and VLOCLK can be active during LPM4..." Go
  • Added the INTERRUPT VECTOR REGISTER column, moved register names from the INTERRUPT FLAG column, and corrected interrupt flag names as necessary in Table 9-4, Interrupt Sources, Flags, Vectors, and Signatures Go
  • Corrected the interrupt flag bit numbers for I/O ports P4 to P9 (changed PxIFG.2 to PxIFG.7) in Table 9-4, Interrupt Sources, Flags, and Vectors Go
  • Corrected typo in "PySEL0.x" header row in Table 9-24, I/O Function Selection Go
  • Corrected the eUSCI module name (changed from eUSCI_A3 to eUSCI_A2) in the note "Direction controlled by eUSCI_A2 module" in Table 9-31, Port P5 (P5.0 to P5.7) Pin Functions Go
  • Corrected the address range for "Main: interrupt vectors" in Table 9-47, Memory Organization Go

Changes from revision B to revision C

Changes from December 16, 2017 to September 25, 2018

  • Updated Section 6.1, Related Products Go
  • Added note (1) to Section 8.13.1.2, SVS Go
  • Changed capacitor value from 4.7 µF to 470 nF in Figure 10-10, ADC12_B Grounding and Noise Considerations Go
  • Changed capacitor value from 4.7 µF to 470 nF in the last paragraph of Section 10.2.1.2, Design Requirements Go
  • Updated text and figure in Section 11.2, Device Nomenclature Go

Changes from revision A to revision B

Changes from September 26, 2017 to December 15, 2017

  • Changed document status to Production DataGo
  • Added Section 6.1, Related Products Go
  • Updated Section 8 Specifications with data for production siliconGo

Changes from initial release to revision A

Changes from June 2, 2017 to September 25, 2017

  • Changed maximum frequency to 2.5 MHz in the list item "Ability to directly interface standard ultrasonic sensors (Up to 2.5 MHz)" in Section 1, Features Go
  • Throughout document, removed mention of capacitive-touch capability on I/O pinsGo
  • Updated Section 8 Specifications Go

6 Device Comparison

Table 6-1 summarizes the available family members.

Table 6-1 Device Comparison
DEVICE(1)(2) FRAM (KB) SRAM (KB) CLOCK SYSTEM LEA USS USSXT MTIF ADC12_B (Channels) Comp_E (Channels) Timer_A(3) Timer_B(4) eUSCI_A(5) eUSCI_B(6) AES BSL I/Os PACKAGE
MSP430FR6047 256 8 DCO
HFXT
LFXT		 Yes Yes Yes 16 external, 2 internal 16 3, 3(7)
2, 2,2(8)		 7 4 2 Yes UART 76 100 PZ (LQFP)
MSP430FR60471 256 8 DCO
HFXT
LFXT		 Yes Yes Yes 16 external, 2 internal 16 3, 3(7)
2, 2,2(8)		 7 4 2 Yes I2C 76 100 PZ (LQFP)
MSP430FR6037 256 8 DCO
HFXT
LFXT		 Yes No Yes 16 external, 2 internal 16 3, 3(7)
2, 2,2(8)		 7 4 2 Yes UART 76 100 PZ (LQFP)
MSP430FR60371 256 8 DCO
HFXT
LFXT		 Yes No Yes 16 external, 2 internal 16 3, 3(7)
2, 2,2(8)		 7 4 2 Yes I2C 76 100 PZ (LQFP)
MSP430FR6045 128 8 DCO
HFXT
LFXT		 Yes Yes Yes 16 external, 2 internal 16 3, 3(7)
2, 2,2(8)		 7 4 2 Yes UART 76 100 PZ (LQFP)
MSP430FR6035 128 8 DCO
HFXT
LFXT		 Yes No Yes 16 external, 2 internal 16 3, 3(7)
2, 2,2(8)		 7 4 2 Yes UART 76 100 PZ (LQFP)
(1) For the most current package and ordering information, see the Package Option Addendum in Section 12, or see the TI website at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having three capture/compare registers and PWM output generators and the second instantiation having five capture/compare registers and PWM output generators, respectively.
(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having three capture/compare registers and PWM output generators and the second instantiation having five capture/compare registers and PWM output generators, respectively.
(5) eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.
(6) eUSCI_B supports I2C with multiple slave addresses and SPI.
(7) Timers TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.
(8) Timers TA2 and TA3 provide only internal capture/compare inputs and only internal PWM outputs (if any) whereas Timer TA4 provides internal, external capture/compare inputs and internal, external PWM outputs.

6.1 Related Products

For information about other devices in this family of products or related products, see the following links.

TI 16-bit and 32-bit microcontrollers

High-performance, low-power solutions to enable the autonomous future

Products for MSP430 ultra-low-power sensing & measurement microcontrollers

One platform. One ecosystem. Endless possibilities.

Reference designs

Find reference designs leveraging the best in TI technology – from analog and power management to embedded processors.

7 Terminal Configuration and Functions

7.1 Pin Diagrams

Figure 7-1 and Figure 7-2 show the pinouts of the 100-pin PZ packages.

GUID-66BD34FD-4FD0-44CF-B6E7-0906F5600C78-low.gif
On devices with UART BSL: P2.0 is BSLTX, P2.1 is BSLRX
On devices with I2C BSL: P1.6 is BSLSDA, P1.7 is BSLSCL
Figure 7-1 MSP430FR604x 100-Pin PZ Package (Top View)
GUID-62E62E83-8B58-44B9-BFE6-E54985C9C98F-low.gif
On devices with UART BSL: P2.0 is BSLTX, P2.1 is BSLRX
On devices with I2C BSL: P1.6 is BSLSDA, P1.7 is BSLSCL
Figure 7-2 MSP430FR603x 100-Pin PZ Package (Top View)

7.2 Pin Attributes

Table 7-1 lists the attributes of each pin.

Table 7-1 Pin Attributes
PIN NUMBERSIGNAL NAME(1)(4)SIGNAL TYPE(2)BUFFER TYPE(3)POWER SOURCE(5)RESET STATE AFTER BOR(7)
1P2.2I/OLVCMOSDVCCOFF
COUTOLVCMOSDVCC–
UCA0CLKI/OLVCMOSDVCC–
A14IAnalogDVCC–
C14IAnalogDVCC–
2P2.3I/OLVCMOSDVCCOFF
TA0.0I/OLVCMOSDVCC–
UCA0STEI/OLVCMOSDVCC–
A15IAnalogDVCC–
C15IAnalogDVCC–
3P1.0I/OLVCMOSDVCCOFF
UCA1CLKI/OLVCMOSDVCC–
TA1.0I/OLVCMOSDVCC–
A0IAnalogDVCC–
C0IAnalogDVCC–
VREF-OAnalogDVCC–
VeREF-IAnalogDVCC–
4P1.1I/OLVCMOSDVCCOFF
UCA1STEI/OLVCMOSDVCC–
TA4.0I/OLVCMOSDVCC–
A1IAnalogDVCC–
C1IAnalogDVCC–
VREF+OAnalogDVCC–
VeREF+IAnalogDVCC–
5AVSS2PPower–N/A
6PJ.4I/OLVCMOSDVCCOFF
LFXINIAnalogDVCC–
7PJ.5I/OLVCMOSDVCCOFF
LFXOUTOAnalogDVCC–
8AVSS3PPower–N/A
9PJ.6I/OLVCMOSDVCC–
HFXINIAnalogDVCC–
10PJ.7I/OLVCMOSDVCCOFF
HFXOUTOAnalogDVCC–
11AVSS4PPower–N/A
12P1.4I/OLVCMOSDVCCOFF
TB0.4I/OLVCMOSDVCC–
UCB0STEI/OLVCMOSDVCC–
A2IAnalogDVCC–
C2IAnalogDVCC–
13P1.5I/OLVCMOSDVCCOFF
TB0.5I/OLVCMOSDVCC–
UCB0CLKI/OLVCMOSDVCC–
A3IAnalogDVCC–
C3IAnalogDVCC–
14P1.6I/OLVCMOSDVCCOFF
UCB0SIMOI/OLVCMOSDVCC–
UCB0SDAI/OLVCMOSDVCC–
A4IAnalogDVCC–
C4IAnalogDVCC–
15P1.7I/OLVCMOSDVCCOFF
USSTRGILVCMOSDVCC–
UCB0SOMII/OLVCMOSDVCC–
UCB0SCLI/OLVCMOSDVCC–
A5IAnalogDVCC–
C5IAnalogDVCC–
16P2.0I/OLVCMOSDVCCOFF
UCA0TXDOLVCMOSDVCC–
UCA0SIMOI/OLVCMOSDVCC–
A6IAnalogDVCC–
C6IAnalogDVCC–
17P2.1I/OLVCMOSDVCCOFF
UCA0RXDILVCMOSDVCC–
UCA0SOMII/OLVCMOSDVCC–
A7IAnalogDVCC–
C7IAnalogDVCC–
18P1.2I/OLVCMOSDVCCOFF
UCA1TXDOLVCMOSDVCC–
UCA1SIMOI/OLVCMOSDVCC–
A8IAnalogDVCC–
C8IAnalogDVCC–
19P1.3I/OLVCMOSDVCCOFF
UCA1RXDILVCMOSDVCC–
UCA1SOMII/OLVCMOSDVCC–
A9IAnalogDVCC–
C9IAnalogDVCC–
20TESTILVCMOSDVCCPD
SBWTCKILVCMOSDVCC–
21RSTI/OLVCMOSDVCCPU
NMIILVCMOSDVCC–
SBWTDIOI/OLVCMOSDVCC–
22PJ.0I/OLVCMOSDVCCOFF
TDOOLVCMOSDVCC–
ACLKOLVCMOSDVCC–
SRSCG1OLVCMOSDVCC–
DMAE0ILVCMOSDVCC–
C10IAnalogDVCC–
23PJ.1I/OLVCMOSDVCCOFF
TDIILVCMOSDVCC–
TCLKILVCMOSDVCC–
SMCLKOLVCMOSDVCC–
SRSCG0OLVCMOSDVCC–
TA4CLKILVCMOSDVCC–
C11IAnalogDVCC–
24PJ.2I/OLVCMOSDVCCOFF
TMSILVCMOSDVCC–
MCLKOLVCMOSDVCC–
SROSCOFFOLVCMOSDVCC–
TB0OUTHILVCMOSDVCC–
C12IAnalogDVCC–
25PJ.3I/OLVCMOSDVCCOFF
TCKILVCMOSDVCC–
RTCCLKOLVCMOSDVCC–
SRCPUOFFOLVCMOSDVCC–
TB0.6I/OLVCMOSDVCC–
C13IAnalogDVCC–
26DVSS1PPower–N/A
27DVCC1PPower–N/A
28P2.4I/OLVCMOSDVCCOFF
TA0CLKILVCMOSDVCC–
TB0CLKILVCMOSDVCC–
TA1CLKILVCMOSDVCC–
S32OAnalogDVCC–
29P2.5I/OLVCMOSDVCCOFF
TA4.0I/OLVCMOSDVCC–
S31OAnalogDVCC–
30P2.6I/OLVCMOSDVCCOFF
TA4.1I/OLVCMOSDVCC–
S30OAnalogDVCC–
31P3.0I/OLVCMOSDVCCOFF
TB0.0I/OLVCMOSDVCC–
S29OAnalogDVCC–
32P3.1I/OLVCMOSDVCCOFF
TB0.1OLVCMOSDVCC–
S28OAnalogDVCC–
33P3.2I/OLVCMOSDVCCOFF
TB0.2OLVCMOSDVCC–
S27OAnalogDVCC–
34P3.3I/OLVCMOSDVCCOFF
TB0.3I/OLVCMOSDVCC–
S26OAnalogDVCC–
35P3.4I/OLVCMOSDVCCOFF
TB0OUTHILVCMOSDVCC–
S25OAnalogDVCC–
36P3.5I/OLVCMOSDVCCOFF
TB0.4I/OLVCMOSDVCC–
S24OAnalogDVCC–
37P3.6I/OLVCMOSDVCCOFF
TB0.5I/OLVCMOSDVCC–
S23OAnalogDVCC–
38P3.7I/OLVCMOSDVCCOFF
TB0.6I/OLVCMOSDVCC–
S22OAnalogDVCC–
39P2.7I/OLVCMOSDVCCOFF
TA0.0I/OLVCMOSDVCC–
S21OAnalogDVCC–
40P9.0I/OLVCMOSDVCCOFF
TA1.0I/OLVCMOSDVCC–
S20OAnalogDVCC–
41P9.1I/OLVCMOSDVCCOFF
SMCLKOLVCMOSDVCC–
S19OAnalogDVCC–
42P9.2I/OLVCMOSDVCCOFF
MCLKOLVCMOSDVCC–
S18OAnalogDVCC–
43P9.3I/OLVCMOSDVCCOFF
ACLKOLVCMOSDVCC–
S17OAnalogDVCC–
44P4.0I/OLVCMOSDVCCOFF
RTCCLKOLVCMOSDVCC–
S16OAnalogDVCC–
45P4.1I/OLVCMOSDVCCOFF
UCA0CLKI/OLVCMOSDVCC–
S15OAnalogDVCC–
46P4.2I/OLVCMOSDVCCOFF
UCA0STEI/OLVCMOSDVCC–
S14OAnalogDVCC–
47P4.3I/OLVCMOSDVCCOFF
UCA0TXDOLVCMOSDVCC–
UCA0SIMOI/OLVCMOSDVCC–
S13OAnalogDVCC–
48P4.4I/OLVCMOSDVCCOFF
UCA0RXDILVCMOSDVCC–
UCA0SOMII/OLVCMOSDVCC–
S12OAnalogDVCC–
49P4.5I/OLVCMOSDVCCOFF
TA0CLKILVCMOSDVCC–
TA1CLKILVCMOSDVCC–
S11OAnalogDVCC–
50P4.6I/OLVCMOSDVCCOFF
TB0CLKILVCMOSDVCC–
TA4CLKILVCMOSDVCC–
S10OAnalogDVCC–
51DVSS2PPower–N/A
52DVCC2PPower–N/A
53P4.7I/OLVCMOSDVCCOFF
DMAE0ILVCMOSDVCC–
S9OAnalogDVCC–
54P5.0I/OLVCMOSDVCCOFF
UCA2TXDOLVCMOSDVCC–
UCA2SIMOI/OLVCMOSDVCC–
S8OAnalogDVCC–
55P5.1I/OLVCMOSDVCCOFF
UCA2RXDILVCMOSDVCC–
UCA2SOMII/OLVCMOSDVCC–
S7OAnalogDVCC–
56P5.2I/OLVCMOSDVCCOFF
UCA2CLKI/OLVCMOSDVCC–
S6OAnalogDVCC–
57P5.3I/OLVCMOSDVCCOFF
UCA2STEI/OLVCMOSDVCC–
S5OAnalogDVCC–
58P5.4I/OLVCMOSDVCCOFF
UCB1CLKI/OLVCMOSDVCC–
S4OAnalogDVCC–
59P5.5I/OLVCMOSDVCCOFF
TA0CLKILVCMOSDVCC–
UCB1SIMOI/OLVCMOSDVCC–
UCB1SDAI/OLVCMOSDVCC–
S3OAnalogDVCC–
60P5.6I/OLVCMOSDVCCOFF
UCB1SOMII/OLVCMOSDVCC–
UCB1SCLI/OLVCMOSDVCC–
S2OAnalogDVCC–
61P5.7I/OLVCMOSDVCCOFF
UCB1STEI/OLVCMOSDVCC–
S1OAnalogDVCC–
62P6.0I/OLVCMOSDVCCOFF
COUTILVCMOSDVCC–
S0OAnalogDVCC–
63P6.4I/OLVCMOSDVCCOFF
COM0OAnalogDVCC–
64P6.5I/OLVCMOSDVCCOFF
COM1OAnalogDVCC–
65P6.6I/OLVCMOSDVCCOFF
COM2OAnalogDVCC–
S38OAnalogDVCC–
66P6.7I/OLVCMOSDVCCOFF
COM3OAnalogDVCC–
S37OAnalogDVCC–
67P7.0I/OLVCMOSDVCCOFF
UCA2TXDOLVCMOSDVCC–
UCA2SIMOI/OLVCMOSDVCC–
ACLKOLVCMOSDVCC–
COM4OAnalogDVCC–
S36OAnalogDVCC–
68P7.1I/OLVCMOSDVCCOFF
UCA2RXDILVCMOSDVCC–
UCA2SOMII/OLVCMOSDVCC–
SMCLKOLVCMOSDVCC–
COM5OAnalogDVCC–
S35OAnalogDVCC–
69P7.2I/OLVCMOSDVCCOFF
UCA2CLKI/OLVCMOSDVCC–
TB0.0I/OLVCMOSDVCC–
COM6OAnalogDVCC–
S34OAnalogDVCC–
70P7.3I/OLVCMOSDVCCOFF
UCA2STEI/OLVCMOSDVCC–
TB0.1I/OLVCMOSDVCC–
COM7OAnalogDVCC–
S33OAnalogDVCC–
71P6.1I/OLVCMOSDVCCOFF
R03I/OAnalogDVCC–
72P6.2I/OLVCMOSDVCCOFF
R13I/OAnalogDVCC–
LCDREFIAnalog-–
73P6.3I/OLVCMOSDVCCOFF
R23I/OAnalogDVCC–
74R33I/OAnalogDVCC-
LCDCAPI/OAnalogDVCC–
75DVSS3PPower–N/A
76DVCC3PPower–N/A
77P7.4I/OLVCMOSDVCCOFF
TA0.1I/OLVCMOSDVCC–
MTIF_OUT_INI/OLVCMOSDVCC–
78P7.5I/OLVCMOSDVCCOFF
TA1.1I/OLVCMOSDVCC–
MTIF_PIN_ENILVCMOSDVCC–
79P8.0I/OLVCMOSDVCCOFF
UCA3STEI/OLVCMOSDVCC–
TB0.2I/OLVCMOSDVCC–
DMAE0ILVCMOSDVCC–
80P8.1I/OLVCMOSDVCCOFF
UCA3CLKI/OLVCMOSDVCC–
TB0.3I/OLVCMOSDVCC–
TB0OUTHILVCMOSDVCC–
81P8.2I/OLVCMOSDVCCOFF
UCA3RXDOLVCMOSDVCC–
UCA3SOMII/OLVCMOSDVCC–
MCLKOLVCMOSDVCC–
82P8.3I/OLVCMOSDVCCOFF
UCA3TXDOLVCMOSDVCC–
UCA3SIMOI/OLVCMOSDVCC–
RTCCLKOLVCMOSDVCC–
83P7.6I/OLVCMOSDVCCOFF
TA4.1I/OLVCMOSDVCC–
DMAE0ILVCMOSDVCC–
COUTOLVCMOSDVCC–
84P7.7I/OLVCMOSDVCCOFF
TA0.2I/OLVCMOSDVCC–
TB0OUTHILVCMOSDVCC–
COUTOLVCMOSDVCC–
85CH1_INIAnalogPVCC–
86CH1_OUTOAnalogPVCC–
87PVSSPPower–N/A
88PVCCPPower–N/A
89PVSSPPower–N/A
90CH0_OUTOAnalogPVCC–
91CH0_INIAnalogPVCC–
92P8.4I/OLVCMOSDVCCOFF
UCB1CLKI/OLVCMOSDVCC–
TA1.2I/OLVCMOSDVCC–
A10IAnalogDVCC–
93P8.5I/OLVCMOSDVCCOFF
UCB1SIMOI/OLVCMOSDVCC–
UCB1SDAI/OLVCMOSDVCC–
A11IAnalogDVCC–
94P8.6I/OLVCMOSDVCCOFF
UCB1SOMII/OLVCMOSDVCC–
UCB1SCLI/OLVCMOSDVCC–
A12IAnalogDVCC–
95P8.7I/OLVCMOSDVCCOFF
UCB1STEI/OLVCMOSDVCC–
USSXT_BOUTI/OLVCMOSDVCC–
A13IAnalogDVCC–
96AVSS5PPower–N/A
97USSXTIN(6)IAnalog1.5V–
98USSXTOUT(6)OAnalog1.5V–
99AVSS1PPower–N/A
100AVCC1PPower–N/A
(1) The signal that is listed first for each pin is the reset default pin name.
(2) Signal Types: I = Input, O = Output, I/O = Input or Output.
(3) Buffer Types: LVCMOS, Analog, or Power (see Table 7-3 for details)
(4) To determine the pin mux encodings for each pin, see Section 9.14.
(5) The power source shown in this table is the I/O power source, which may differ from the module power source.
(6) Do not connect USSXTIN and USSXTOUT pins to AVCC nor to DVCC. USSXTIN does not support bypass mode, so do not drive an external clock on the USSXTIN pin.
(7) Reset States:
OFF = High impedance with Schmitt-trigger input and pullup or pulldown (if available) disabled
PU = Pullup is enabled
PD = Pulldown is enabled
N/A = Not applicable

7.3 Signal Descriptions

Section 7.3 describes the signals.

Table 7-2 Signal Descriptions
FUNCTION SIGNAL NAME PIN NO. PIN TYPE(1) DESCRIPTION
PZ
ADC A0 3 I ADC analog input A0
A1 4 I ADC analog input A1
A2 12 I ADC analog input A2
A3 13 I ADC analog input A3
A4 14 I ADC analog input A4
A5 15 I ADC analog input A5
A6 16 I ADC analog input A6
A7 17 I ADC analog input A7
A8 18 I ADC analog input A8
A9 19 I ADC analog input A9
A10 92 I ADC analog input A10
A11 93 I ADC analog input A11
A12 94 I ADC analog input A12
A13 95 I ADC analog input A13
A14 1 I ADC analog input A14
A15 2 I ADC analog input A15
VREF+ 4 O Output of positive reference voltage
VREF- 3 O Output of negative reference voltage
VeREF+ 4 I Input for an external positive reference voltage to the ADC
VeREF- 3 I Input for an external negative reference voltage to the ADC
Clock ACLK 22, 43, 67 O ACLK output
HFXIN 9 I Input for high-frequency crystal oscillator HFXT
HFXOUT 10 O Output for high-frequency crystal oscillator HFXT
LFXIN 6 I Input for low-frequency crystal oscillator LFXT
LFXOUT 7 O Output of low-frequency crystal oscillator LFXT
MCLK 24, 42, 81 O MCLK output
SMCLK 23, 41, 68 O SMCLK output
Comparator C0 3 I Comparator input C0
C1 4 I Comparator input C1
C2 12 I Comparator input C2
C3 13 I Comparator input C3
C4 14 I Comparator input C4
C5 15 I Comparator input C5
C6 16 I Comparator input C6
C7 17 I Comparator input C7
C8 18 I Comparator input C8
C9 19 I Comparator input C9
C10 22 I Comparator input C10
C11 23 I Comparator input C11
C12 24 I Comparator input C12
C13 25 I Comparator input C13
C14 1 I Comparator input C14
C15 2 I Comparator input C15
COUT 1, 83, 84 O Comparator output
DMA DMAE0 22, 79, 83 I External DMA trigger
Debug SBWTCK 20 I Spy-Bi-Wire input clock
SBWTDIO 21 I/O Spy-Bi-Wire data input/output
SRCPUOFF 25 O Low-power debug: CPU Status register bit CPUOFF
SROSCOFF 24 O Low-power debug: CPU Status register bit OSCOFF
SRSCG0 23 O Low-power debug: CPU Status register bit SCG0
SRSCG1 22 O Low-power debug: CPU Status register bit SCG1
TCK 25 I Test clock
TCLK 23 I Test clock input
TDI 23 I Test data input
TDO 22 O Test data output port
TEST 20 I Test mode pin, selects digital I/O on JTAG pins
TMS 24 I Test mode select
GPIO Port 1 P1.0 3 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P1.1 4 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P1.2 18 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P1.3 19 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P1.4 12 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P1.5 13 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P1.6 14 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P1.7 15 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
GPIO Port 2 P2.0 16 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.1 17 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.2 1 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.3 2 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.4 28 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.5 29 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.6 30 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.7 39 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
GPIO Port 3 P3.0 31 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.1 32 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.2 33 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.3 34 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.4 35 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.5 36 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.6 37 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.7 38 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
GPIO Port 4 P4.0 44 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P4.1 45 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P4.2 46 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P4.3 47 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P4.4 48 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P4.5 49 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P4.6 50 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P4.7 53 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
GPIO Port 5 P5.0 54 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P5.1 55 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P5.2 56 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P5.3 57 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P5.4 58 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P5.5 59 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P5.6 60 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P5.7 61 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
GPIO Port 6 P6.0 62 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P6.1 71 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P6.2 72 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P6.3 73 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P6.4 63 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P6.5 64 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P6.6 65 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P6.7 66 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
GPIO Port 7 P7.0 67 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P7.1 68 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P7.2 69 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P7.3 70 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P7.4 77 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P7.5 78 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P7.6 83 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P7.7 84 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
GPIO Port 8 P8.0 79 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P8.1 80 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P8.2 81 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P8.3 82 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P8.4 92 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P8.5 93 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P8.6 94 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P8.7 95 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
GPIO Port 9 P9.0 40 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P9.1 41 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P9.2 42 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P9.3 43 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
GPIO Port J PJ.0 22 I/O General-purpose digital I/O
PJ.1 23 I/O General-purpose digital I/O
PJ.2 24 I/O General-purpose digital I/O
PJ.3 25 I/O General-purpose digital I/O
PJ.4 6 I/O General-purpose digital I/O
PJ.5 7 I/O General-purpose digital I/O
PJ.6 9 I/O General-purpose digital I/O
PJ.7 10 I/O General-purpose digital I/O
I2C UCB0SCL 15 I/O I2C clock for eUSCI_B0 I2C mode
UCB0SDA 14 I/O I2C data for eUSCI_B0 I2C mode
UCB1SCL 94, 60 I/O I2C clock for eUSCI_B1 I2C mode
UCB1SDA 93, 59 I/O I2C data for eUSCI_B1 I2C mode
LCD COM0 63 O LCD common output COM0 for LCD backplane
COM1 64 O LCD common output COM1 for LCD backplane
COM2 65 O LCD common output COM2 for LCD backplane
COM3 66 O LCD common output COM3 for LCD backplane
COM4 67 O LCD common output COM4 for LCD backplane
COM5 68 O LCD common output COM5 for LCD backplane
COM6 69 O LCD common output COM6 for LCD backplane
COM7 70 O LCD common output COM7 for LCD backplane
LCDCAP 74 I/O LCD capacitor connection
CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
LCDREF 72 I External reference voltage input for regulated LCD voltage
R03 71 I/O Input/output port of lowest analog LCD voltage (V5)
R13 72 I/O Input/output port of third most positive analog LCD voltage (V3 or V4)
R23 73 I/O Input/output port of second most positive analog LCD voltage (V2)
R33 74 I/O Input/output port of most positive analog LCD voltage (V1)
CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
S0 62 O LCD segment output
S1 61 O LCD segment output
S2 60 O LCD segment output
S3 59 O LCD segment output
S4 58 O LCD segment output
S5 57 O LCD segment output
S6 56 O LCD segment output
S7 55 O LCD segment output
S8 54 O LCD segment output
S9 53 O LCD segment output
S10 50 O LCD segment output
S11 49 O LCD segment output
S12 48 O LCD segment output
S13 47 O LCD segment output
S14 46 O LCD segment output
S15 45 O LCD segment output
S16 44 O LCD segment output
S17 43 O LCD segment output
S18 42 O LCD segment output
S19 41 O LCD segment output
S20 40 O LCD segment output
S21 39 O LCD segment output
S22 38 O LCD segment output
S23 37 O LCD segment output
S24 36 O LCD segment output
S25 35 O LCD segment output
S26 34 O LCD segment output
S27 33 O LCD segment output
S28 32 O LCD segment output
S29 31 O LCD segment output
LCD (continued) S30 30 O LCD segment output
S31 29 O LCD segment output
S32 28 O LCD segment output
S33 70 O LCD segment output
S34 69 O LCD segment output
S35 68 O LCD segment output
S36 67 O LCD segment output
S37 66 O LCD segment output
S38 65 O LCD segment output
MTIF MTIF_PIN_EN 78 I Meter test interface pin enable
MTIF_OUT_IN 77 I/O Meter test interface input and output
Power AVCC1 100 P Analog power supply
AVSS1 99 P Analog ground supply
AVSS2 5 P Analog ground supply
AVSS3 8 P Analog ground supply
AVSS4 11 P Analog ground supply
AVSS5 96 P Analog ground supply
DVCC1 27 P Digital power supply
DVCC2 52 P Digital power supply
DVCC3 76 P Digital power supply
DVSS1 26 P Digital ground supply
DVSS2 51 P Digital ground supply
DVSS3 75 P Digital ground supply
PVCC 88 P USS power supply
PVSS 87, 89 P USS ground supply
RTC RTCCLK 25, 44, 82 O RTC clock calibration output
SPI UCA0CLK 1, 45 I/O Clock signal input for eUSCI_A0 SPI slave mode
Clock signal output for eUSCI_A0 SPI master mode
UCA0SIMO 16, 47 I/O Slave in/master out for eUSCI_A0 SPI mode
UCA0SOMI 17, 48 I/O Slave out/master in for eUSCI_A0 SPI mode
UCA0STE 2, 46 I/O Slave transmit enable for eUSCI_A0 SPI mode
UCA1CLK 3 I/O Clock signal input for eUSCI_A1 SPI slave mode
Clock signal output for eUSCI_A1 SPI master mode
UCA1SIMO 18 I/O Slave in/master out for eUSCI_A1 SPI mode
UCA1SOMI 19 I/O Slave out/master in for eUSCI_A1 SPI mode
UCA1STE 4 I/O Slave transmit enable for eUSCI_A1 SPI mode
UCA2CLK 69, 56 I/O Clock signal input for eUSCI_A2 SPI slave mode
Clock signal output for eUSCI_A2 SPI master mode
UCA2SIMO 67, 54 I/O Slave in/master out for eUSCI_A2 SPI mode
UCA2SOMI 68, 55 I/O Slave out/master in for eUSCI_A2 SPI mode
UCA2STE 70, 57 I/O Slave transmit enable for eUSCI_A2 SPI mode
UCA3CLK 80 I/O Clock signal input for eUSCI_A3 SPI slave mode
Clock signal output for eUSCI_A3 SPI master mode
UCA3SIMO 82 I/O Slave in/master out for eUSCI_A3 SPI mode
UCA3SOMI 81 I/O Slave out/master in for eUSCI_A3 SPI mode
UCA3STE 79 I/O Slave transmit enable for eUSCI_A3 SPI mode
UCB0CLK 13 I/O Clock signal input for eUSCI_B0 SPI slave mode
Clock signal output for eUSCI_B0 SPI master mode
UCB0SIMO 14 I/O Slave in/master out for eUSCI_B0 SPI mode
UCB0SOMI 15 I/O Slave out/master in for eUSCI_B0 SPI mode
UCB0STE 12 I/O Slave transmit enable for eUSCI_B0 SPI mode
UCB1CLK 92, 58 I/O Clock signal input for eUSCI_B1 SPI slave mode
Clock signal output for eUSCI_B1 SPI master mode
UCB1SIMO 93, 59 I/O Slave in/master out for eUSCI_B1 SPI mode
UCB1SOMI 94, 60 I/O Slave out/master in for eUSCI_B1 SPI mode
UCB1STE 95, 61 I/O Slave transmit enable for eUSCI_B1 SPI mode
System NMI 21 I Nonmaskable interrupt input
RST 21 I/O Reset input active low
Timer TA0.0 2 I/O TA0 CCR0 capture: CCI0A input, compare: Out0
TA0.0 39 I/O TA0 CCR0 capture: CCI0B input, compare: Out0
TA0.1 77 I/O TA0 CCR1 capture: CCI1A input, compare: Out1
TA0.2 84 I/O TA0 CCR2 capture: CCI2A input, compare: Out2
TA0CLK 28, 49, 59 I TA0 input clock
TA1.0 3 I/O TA1 CCR0 capture: CCI0A input, compare: Out0
TA1.0 40 I/O TA1 CCR0 capture: CCI0B input, compare: Out0
TA1.1 78 I/O TA1 CCR1 capture: CCI1A input, compare: Out1
TA1.2 92 I/O TA1 CCR2 capture: CCI2A input, compare: Out2
TA1CLK 28, 49 I TA1 input clock
TA4.0 4 I/O TA4 CCR0 capture: CCI0A input, compare: Out0
TA4.0 29 I/O TA4 CCR0 capture: CCI0B input, compare: Out0
TA4.1 30 I/O TA4CCR1 capture: CCI1B input, compare: Out1
TA4.1 83 I/O TA4 CCR1 capture: CCI1A input, compare: Out1
TA4CLK 23, 50 I TA4 input clock
TB0.0 31 I/O TB0 CCR0 capture: CCI0B input, compare: Out0
TB0.0 69 I/O TB0 CCR0 capture: CCI0A input, compare: Out0
TB0.1 32 I/O TB0 CCR1 capture: CCI1A input, compare: Out1
TB0.1 70 O TB0 CCR1 compare: Out1
TB0.2 33 I/O TB0 CCR2 capture: CCI2A input, compare: Out2
TB0.2 79 O TB0 CCR2 compare: Out2
TB0.3 34 I/O TB0 CCR3 capture: CCI3A input, compare: Out3
TB0.3 80 I/O TB0 CCR3 capture: CCI3B input, compare: Out3
TB0.4 12 I/O TB0 CCR4 capture: CCI4A input, compare: Out4
TB0.4 36 I/O TB0 CCR4 capture: CCI4B input, compare: Out4
TB0.5 13 I/O TB0 CCR5 capture: CCI5A input, compare: Out5
TB0.5 37 I/O TB0CCR5 capture: CCI5B input, compare: Out5
TB0.6 25 I/O TB0 CCR6 capture: CCI6B input, compare: Out6
TB0.6 38 I/O TB0 CCR6 capture: CCI6A input, compare: Out6
TB0CLK 28, 50 I TB0 clock input
TB0OUTH 24, 35, 80, 84 I Switch all PWM outputs high impedance input – TB0
UART UCA0RXD 17, 48 I Receive data for eUSCI_A0 UART mode
UCA0TXD 16, 47 O Transmit data for eUSCI_A0 UART mode
UCA1RXD 19 I Receive data for eUSCI_A1 UART mode
UCA1TXD 18 O Transmit data for eUSCI_A1 UART mode
UCA2RXD 68, 55 I Receive data for eUSCI_A2 UART mode
UCA2TXD 67, 54 O Transmit data for eUSCI_A2 UART mode
UCA3RXD 81 I Receive data for eUSCI_A3 UART mode
UCA3TXD 82 O Transmit data for eUSCI_A3 UART mode
USS USSTRG 15 I USS trigger
USSXTIN 97 I Input for crystal or resonator of oscillator USSXT
USSXTOUT 98 O Output for crystal or resonator of oscillator USSXT
USSXT_BOUT 95 O Buffered output clock of USSXT
CH0_IN 91 I USS channel 0 RX
CH0_OUT 90 I/O USS channel 0 TX
CH1_IN 85 I USS channel 1 RX
CH1_OUT 86 I/O USS channel 1 TX
(1) I = input, O = output, P = power

7.4 Pin Multiplexing

Pin multiplexing for these devices is controlled by both register settings and operating modes (for example, if the device is in test mode). For details of the settings for each pin and diagrams of the multiplexed ports, see Section 9.14.

7.5 Buffer Type

Table 7-3 describes the buffer types that are referenced in Table 7-1.

Table 7-3 Buffer Type
BUFFER TYPE (STANDARD)NOMINAL VOLTAGEHYSTERESISPULLUP (PU)
OR
PULLDOWN (PD)		NOMINAL PU OR PD STRENGTH (µA)OUTPUT DRIVE STRENGTH (mA)OTHER CHARACTERISTICS
Analog(2)3.0 VNN/AN/AN/ASee analog modules in Section 8 for details.
LVCMOS3.0 VY(1)ProgrammableSee Section 8.13.5.See Section 8.13.5.
Power (DVCC)(3)3.0 VNN/AN/AN/ASVS enables hysteresis on DVCC.
Power (AVCC)(3)3.0 VNN/AN/AN/A
Power (PVCC)(3)3.0 VNN/AN/AN/A
Power (DVSS and AVSS)(3)0 VNN/AN/AN/A
(1) Only for input pins
(2) This is a switch, not a buffer.
(3) This is supply input, not a buffer.

7.6 Connection of Unused Pins

Table 7-4 lists the correct termination of unused pins.

Table 7-4 Connection of Unused Pins
PIN(1) POTENTIAL COMMENT
AVCC DVCC
PVCC DVCC
AVSS DVSS
PVSS DVSS
CHx_IN, CHx_OUT DVSS
USSXTIN DVSS Do not connect to DVCC, AVCC, or PVCC
USSXTOUT Open
Px.0 to Px.7 Open Switched to port function, output direction (PxDIR.n = 1)
RST/NMI/SBWTDIO DVCC or VCC 47-kΩ pullup or internal pullup selected with 10-nF (2.2-nF(2)) pulldown
PJ.0/TDO
PJ.1/TDI
PJ.2/TMS
PJ.3/TCK		 Open The JTAG pins are shared with general-purpose I/O function (PJ.x). If these pins are not used, set them to port function, output direction. If used as JTAG pins, leave them open.
TEST Open This pin always has an internal pulldown enabled.
(1) For any unused pin with a secondary function that is shared with general-purpose I/O, follow the guidelines for the Px.0 to Px.7 pins.
(2) The pulldown capacitor must not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG mode with TI tools like FET interfaces or GANG programmers.

 
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