• Menu
  • Product
  • Email
  • PDF
  • Order now
  • MSP430FR604x(1), MSP430FR603x(1) Ultrasonic Sensing MSP430™ Microcontrollers for Water‑Metering Applications

    • SLASEB7D June   2017  – December 2020

      PRODUCTION DATA  

  • CONTENTS
  • SEARCH
  • MSP430FR604x(1), MSP430FR603x(1) Ultrasonic Sensing MSP430™ Microcontrollers for Water‑Metering Applications
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagrams
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Buffer Type
    6. 7.6 Connection of Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Typical Characteristics, Active Mode Supply Currents
    6. 8.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 8.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 8.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 8.9  Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
    10. 8.10 Typical Characteristics, Low-Power Mode Supply Currents
    11. 8.11 Typical Characteristics, Current Consumption per Module (1)
    12. 8.12 Thermal Resistance Characteristics for 100-Pin LQFP (PZ) Package
    13. 8.13 Timing and Switching Characteristics
      1. 8.13.1  Power Supply Sequencing
        1. 8.13.1.1 Brownout and Device Reset Power Ramp Requirements
        2. 8.13.1.2 SVS
      2. 8.13.2  Reset Timing
        1. 8.13.2.1 Reset Input
      3. 8.13.3  Clock Specifications
        1. 8.13.3.1 Low-Frequency Crystal Oscillator, LFXT
        2. 8.13.3.2 High-Frequency Crystal Oscillator, HFXT
        3. 8.13.3.3 DCO
        4. 8.13.3.4 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. 8.13.3.5 Module Oscillator (MODOSC)
      4. 8.13.4  Wake-up Characteristics
        1. 8.13.4.1 Wake-up Times From Low-Power Modes and Reset
        2. 8.13.4.2 Typical Wake-up Charges
        3. 8.13.4.3 Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 8.13.5  Digital I/Os
        1. 8.13.5.1 Digital Inputs
        2. 8.13.5.2 Digital Outputs
        3. 8.13.5.3 Typical Characteristics, Digital Outputs
      6. 8.13.6  LEA
        1. 8.13.6.1 Low-Energy Accelerator (LEA) Performance
      7. 8.13.7  Timer_A and Timer_B
        1. 8.13.7.1 Timer_A
        2. 8.13.7.2 Timer_B
      8. 8.13.8  eUSCI
        1. 8.13.8.1 eUSCI (UART Mode) Clock Frequency
        2. 8.13.8.2 eUSCI (UART Mode) Switching Characteristics
        3. 8.13.8.3 eUSCI (SPI Master Mode) Clock Frequency
        4. 8.13.8.4 eUSCI (SPI Master Mode) Switching Characteristics
        5. 8.13.8.5 eUSCI (SPI Master Mode) Timing Diagrams
        6. 8.13.8.6 eUSCI (SPI Slave Mode) Switching Characteristics
        7. 8.13.8.7 eUSCI (SPI Slave Mode) Timing Diagrams
        8. 8.13.8.8 eUSCI (I2C Mode) Switching Characteristics
        9. 8.13.8.9 eUSCI (SPI Slave Mode) Timing Diagrams
      9. 8.13.9  Segment LCD Controller
        1. 8.13.9.1 LCD_C Recommended Operating Conditions
        2. 8.13.9.2 LCD_C Electrical Characteristics
      10. 8.13.10 ADC12_B
        1. 8.13.10.1 12-Bit ADC, Power Supply and Input Range Conditions
        2. 8.13.10.2 12-Bit ADC, Timing Parameters
        3. 8.13.10.3 12-Bit ADC, Linearity Parameters
        4. 8.13.10.4 12-Bit ADC, Dynamic Performance With External Reference
        5. 8.13.10.5 12-Bit ADC, Dynamic Performance With Internal Reference
        6. 8.13.10.6 12-Bit ADC, Temperature Sensor and Built-In V1/2
        7. 8.13.10.7 12-Bit ADC, External Reference
        8. 8.13.10.8 Temperature Sensor Typical Characteristics
      11. 8.13.11 Reference
        1. 8.13.11.1 REF, Built-In Reference
      12. 8.13.12 Comparator
        1. 8.13.12.1 Comparator_E
      13. 8.13.13 FRAM
        1. 8.13.13.1 FRAM
      14. 8.13.14 USS
        1. 8.13.14.1 USS Recommended Operating Conditions
        2. 8.13.14.2 USS LDO
        3. 8.13.14.3 USSXTAL
        4. 8.13.14.4 USS HSPLL
        5. 8.13.14.5 USS SDHS
        6. 8.13.14.6 USS PHY Output Stage
        7. 8.13.14.7 USS PHY Input Stage, Multiplexer
        8. 8.13.14.8 USS PGA
        9. 8.13.14.9 USS Bias Voltage Generator
      15. 8.13.15 Emulation and Debug
        1. 8.13.15.1 JTAG and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Ultrasonic Sensing Solution (USS) Module
    4. 9.4  Low-Energy Accelerator (LEA) for Signal Processing
    5. 9.5  Operating Modes
      1. 9.5.1 Peripherals in Low-Power Modes
      2. 9.5.2 Idle Currents of Peripherals in LPM3 and LPM4
    6. 9.6  Interrupt Vector Table and Signatures
    7. 9.7  Bootloader (BSL)
    8. 9.8  JTAG Operation
      1. 9.8.1 JTAG Standard Interface
      2. 9.8.2 Spy-Bi-Wire (SBW) Interface
    9. 9.9  FRAM Controller A (FRCTL_A)
    10. 9.10 RAM
    11. 9.11 Tiny RAM
    12. 9.12 Memory Protection Unit (MPU) Including IP Encapsulation
    13. 9.13 Peripherals
      1. 9.13.1  Digital I/O
      2. 9.13.2  Oscillator and Clock System (CS)
      3. 9.13.3  Power-Management Module (PMM)
      4. 9.13.4  Hardware Multiplier (MPY)
      5. 9.13.5  Real-Time Clock (RTC_C)
      6. 9.13.6  Measurement Test Interface (MTIF)
      7. 9.13.7  Watchdog Timer (WDT_A)
      8. 9.13.8  System Module (SYS)
      9. 9.13.9  DMA Controller
      10. 9.13.10 Enhanced Universal Serial Communication Interface (eUSCI)
      11. 9.13.11 TA0, TA1, and TA4
      12. 9.13.12 TA2 and TA3
      13. 9.13.13 TB0
      14. 9.13.14 ADC12_B
      15. 9.13.15 USS
      16. 9.13.16 Comparator_E
      17. 9.13.17 CRC16
      18. 9.13.18 CRC32
      19. 9.13.19 AES256 Accelerator
      20. 9.13.20 True Random Seed
      21. 9.13.21 Shared Reference (REF)
      22. 9.13.22 LCD_C
      23. 9.13.23 Embedded Emulation
        1. 9.13.23.1 Embedded Emulation Module (EEM) (S Version)
        2. 9.13.23.2 EnergyTrace++ Technology
    14. 9.14 Input/Output Diagrams
      1. 9.14.1  Port Function Select Registers (PySEL1 , PySEL0)
      2. 9.14.2  Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
      3. 9.14.3  Port P1 (P1.2 to P1.7) Input/Output With Schmitt Trigger
      4. 9.14.4  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
      5. 9.14.5  Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
      6. 9.14.6  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      7. 9.14.7  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      8. 9.14.8  Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      9. 9.14.9  Port P6 (P6.0) Input/Output With Schmitt Trigger
      10. 9.14.10 Port P6 (P6.1 to P6.5) Input/Output With Schmitt Trigger
      11. 9.14.11 Port P6 (P6.6 and P6.7) Input/Output With Schmitt Trigger
      12. 9.14.12 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
      13. 9.14.13 Port P7 (P7.4) Input/Output With Schmitt Trigger
      14. 9.14.14 Port P7 (P7.5) Input/Output With Schmitt Trigger
      15. 9.14.15 Port P7 (P7.6 and P7.7) Input/Output With Schmitt Trigger
      16. 9.14.16 Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
      17. 9.14.17 Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger
      18. 9.14.18 Port P9 (P9.0 to P9.3) Input/Output With Schmitt Trigger
      19. 9.14.19 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
      20. 9.14.20 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
      21. 9.14.21 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
    15. 9.15 Device Descriptors (TLV)
    16. 9.16 Memory Map
      1. 9.16.1 Peripheral File Map
    17. 9.17 Identification
      1. 9.17.1 Revision Identification
      2. 9.17.2 Device Identification
      3. 9.17.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1  Power Supply Decoupling and Bulk Capacitors
      2. 10.1.2  External Oscillator (HFXT and LFXT)
      3. 10.1.3  USS Oscillator (USSXT)
      4. 10.1.4  Transducer Connection to the USS Module
      5. 10.1.5  Charge Pump Control of Input Multiplexer
      6. 10.1.6  JTAG
      7. 10.1.7  Reset
      8. 10.1.8  Unused Pins
      9. 10.1.9  General Layout Recommendations
      10. 10.1.10 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 ADC12_B Peripheral
        1. 10.2.1.1 Partial Schematic
        2. 10.2.1.2 Design Requirements
        3. 10.2.1.3 Detailed Design Procedure
        4. 10.2.1.4 Layout Guidelines
      2. 10.2.2 LCD_C Peripheral
        1. 10.2.2.1 Partial Schematic
        2. 10.2.2.2 Design Requirements
        3. 10.2.2.3 Detailed Design Procedure
        4. 10.2.2.4 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Getting Started
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 Support Resources
    6. 11.6 Export Control Notice
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
    9. 11.9 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

DATA SHEET

MSP430FR604x(1), MSP430FR603x(1) Ultrasonic Sensing MSP430™ Microcontrollers for Water‑Metering Applications

1 Features

  • Best-in-class ultrasonic water-flow measurement with ultra-low power consumption
    • <25-ps differential time-of-flight (dTOF) accuracy
    • High-precision time measurement resolution of <5 ps
    • Ability to detect low flow rates (<1 liter per hour)
    • Approximately 3-µA overall current consumption with one measurement per second
  • Compliant to and exceeds ISO 4064, OIML R49, and EN 1434 accuracy standards
  • Ability to directly interface standard ultrasonic sensors (up to 2.5 MHz)
  • Integrated analog front end – ultrasonic sensing solution (USS)
    • Programmable pulse generation (PPG) to generate pulses at different frequencies
    • Integrated physical interface (PHY) with low-impedance (4-Ω) output driver to control input and output channels
    • High-performance high-speed 12-bit sigma-delta ADC (SDHS) with output data rates up to 8 Msps
    • Programmable gain amplifier (PGA) with –6.5 dB to 30.8 dB
    • High-performance phase-locked loop (PLL) with output range of 68 MHz to 80 MHz
  • Metering test interface (MTIF)
    • Pulse generator and pulse counter
    • Pulse rates up to 1016 pulses per second (p/s)
    • Count capacity up to 65535 (16 bits)
    • Operates in LPM3.5 with 200 nA (typical)
  • Low-energy accelerator (LEA)
    • Operation independent of CPU
    • 4KB of RAM shared with CPU
    • Efficient 256-point complex FFT:
      Up to 40× faster than Arm®Cortex®-M0+ core
  • Embedded microcontroller
    • 16-bit RISC architecture up to 16‑MHz clock
    • Wide supply voltage range from 3.6 V down to 1.8 V (minimum supply voltage is restricted by SVS levels, see the SVS specifications)
  • Optimized ultra-low-power modes
    • Active mode: approximately 120 µA/MHz
    • Standby mode with real-time clock (RTC) (LPM3.5): 450 nA
    • Shutdown (LPM4.5): 30 nA
  • Ferroelectric random access memory (FRAM)
    • Up to 256KB of nonvolatile memory
    • Ultra-low-power writes
    • Fast write at 125 ns per word (64KB in 4 ms)
    • Unified memory = program + data + storage in one space
    • 1015 write cycle endurance
    • Radiation resistant and nonmagnetic
  • Intelligent digital peripherals
    • 32-bit hardware multiplier (MPY)
    • 6-channel internal DMA
    • RTC with calendar and alarm functions
    • Six 16-bit timers with up to seven capture/compare registers each
    • 32-bit and 16-bit cyclic redundancy check (CRC)
  • High-performance analog
    • 16-channel analog comparator
    • 12-bit SAR ADC featuring window comparator, internal reference, and sample-and-hold, up to 16 external input channels
    • Integrated LCD driver with contrast control for up to 264 segments
  • Multifunction input/output ports
    • Accessible bit-, byte-, and word-wise (in pairs)
    • Edge-selectable wake from LPM on all ports
    • Programmable pullup and pulldown on all ports
  • Code security and encryption
    • 128- or 256-bit AES security encryption and decryption coprocessor
    • Random number seed for random number generation algorithms
    • IP encapsulation protects memory from external access
    • FRAM provides inherent security advantages
  • Enhanced serial communication
    • Up to four eUSCI_A serial communication ports
      • UART with automatic baud-rate detection
      • IrDA encode and decode
    • Up to two eUSCI_B serial communication ports
      • I2C with multiple-slave addressing
    • Hardware UART or I2C bootloader (BSL)
  • Flexible clock system
    • Fixed-frequency DCO with 10 selectable factory-trimmed frequencies
    • Low-power low-frequency internal clock source (VLO)
    • 32-kHz crystals (LFXT)
    • High-frequency crystals (HFXT)
  • Development tools and software (also see Tools and Software)
    • Ultrasonic Sensing Design Center graphical user interface
    • Ultrasonic sensing software library
    • EVM430-FR6047 water meter evaluation module
    • MSP-TS430PZ100E target socket board for 100-pin package
    • Free professional development environments with EnergyTrace++ technology
    • MSP430Ware™ for MSP430™ microcontrollers
  • Device Comparison summarizes the available device variants and package options
SLASEB77493. The RTC is clocked by a 3.7-pF crystal.

2 Applications

  • Ultrasonic smart water meter
  • Ultrasonic smart heat meter
  • Liquid level sensing
  • Water leak detector

3 Description

The Texas Instruments MSP430FR604x and MSP430FR603x family of ultrasonic sensing and measurement SoCs are powerful, highly integrated microcontrollers (MCUs) that are optimized for water and heat meters. The MSP430FR604x MCUs offer an integrated ultrasonic sensing solution (USS) module, which provides high accuracy for a wide range of flow rates. The USS module helps achieve ultra-low-power metering combined with lower system cost due to maximum integration requiring very few external components. MSP430FR604x and MSP430FR603x MCUs implement a high-speed ADC-based signal acquisition followed by optimized digital signal processing using the integrated low-energy accelerator (LEA) module to deliver a high-accuracy metering solution with ultra-low power optimum for battery-powered metering applications.

The USS module includes a programmable pulse generator (PPG) and a physical interface (PHY) with a low-impedance output driver for optimum sensor excitation and accurate impendence matching to deliver best results for zero-flow drift (ZFD). The module also includes a programmable gain amplifier (PGA) and a high-speed 12-bit 8-Msps sigma-delta ADC (SDHS) for accurate signal acquisition from industry-standard ultrasonic transducers.

Additionally, MSP430FR604x and MSP430FR603x MCUs integrate other peripherals to improve system integration for metering. The devices have a metering test interface (MTIF) module to implement pulse generation to indicate flow measured by the meter. The MSP430FR604x and MSP430FR603x MCUs also have an on-chip 8-mux LCD driver, an RTC, a 12-bit SAR ADC, an analog comparator, an advanced encryption accelerator (AES256), and a cyclic redundancy check (CRC) module.

MSP430FR604x and MSP430FR603x MCUs are supported by an extensive hardware and software ecosystem with reference designs and code examples to get your design started quickly. Development kits include the MSP‑TS430PZ100E 100-pin target development board and EVM430‑FR6047 ultrasonic water flow meter EVM. TI also provides free software including the ultrasonic sensing design center, ultrasonic sensing software library, and MSP430Ware™ software.

TI's MSP430 ultra-low-power (ULP) FRAM microcontroller platform combines uniquely embedded FRAM and a holistic ultra-low-power system architecture, letting system designers increase performance while lowering energy consumption. FRAM technology combines the low-energy fast writes, flexibility, and endurance of RAM with the nonvolatility of flash.

For complete module descriptions, see the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide.

Device Information(1)(2)
PART NUMBER PACKAGE BODY SIZE(3)
MSP430FR6047IPZ
MSP430FR60471IPZ
MSP430FR6045IPZ
MSP430FR6037IPZ
MSP430FR60371IPZ
MSP430FR6035IPZ
LQFP (100) 14 mm × 14 mm
(1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 12, or see the TI website at www.ti.com.
(2) For a comparison of all available device variants, see Section 6.
(3) The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 12.

4 Functional Block Diagrams

Figure 4-1 and Figure 4-2 show the functional block diagrams of the devices.

GUID-B12533C9-F42B-48BA-BBD3-0C35936688A1-low.gif
The device has 8KB of RAM, and 4KB of the RAM is shared with the LEA subsystem.
Figure 4-1 MSP430FR604x Functional Block Diagram
GUID-2A86FA6A-BD94-435B-868F-7DB03FC58BBB-low.gif
The device has 8KB of RAM, and 4KB of the RAM is shared with the LEA subsystem.
Figure 4-2 MSP430FR603x Functional Block Diagram

5 Revision History

Changes from revision C to revision D

Changes from September 26, 2018 to December 1, 2020

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Changed Section 6.1, Related Products Go
  • Added the note that begins "XT1CLK and VLOCLK can be active during LPM4..." Go
  • Added the INTERRUPT VECTOR REGISTER column, moved register names from the INTERRUPT FLAG column, and corrected interrupt flag names as necessary in Table 9-4, Interrupt Sources, Flags, Vectors, and Signatures Go
  • Corrected the interrupt flag bit numbers for I/O ports P4 to P9 (changed PxIFG.2 to PxIFG.7) in Table 9-4, Interrupt Sources, Flags, and Vectors Go
  • Corrected typo in "PySEL0.x" header row in Table 9-24, I/O Function Selection Go
  • Corrected the eUSCI module name (changed from eUSCI_A3 to eUSCI_A2) in the note "Direction controlled by eUSCI_A2 module" in Table 9-31, Port P5 (P5.0 to P5.7) Pin Functions Go
  • Corrected the address range for "Main: interrupt vectors" in Table 9-47, Memory Organization Go

Changes from revision B to revision C

Changes from December 16, 2017 to September 25, 2018

  • Updated Section 6.1, Related Products Go
  • Added note (1) to Section 8.13.1.2, SVS Go
  • Changed capacitor value from 4.7 µF to 470 nF in Figure 10-10, ADC12_B Grounding and Noise Considerations Go
  • Changed capacitor value from 4.7 µF to 470 nF in the last paragraph of Section 10.2.1.2, Design Requirements Go
  • Updated text and figure in Section 11.2, Device Nomenclature Go

Changes from revision A to revision B

Changes from September 26, 2017 to December 15, 2017

  • Changed document status to Production DataGo
  • Added Section 6.1, Related Products Go
  • Updated Section 8 Specifications with data for production siliconGo

Changes from initial release to revision A

Changes from June 2, 2017 to September 25, 2017

  • Changed maximum frequency to 2.5 MHz in the list item "Ability to directly interface standard ultrasonic sensors (Up to 2.5 MHz)" in Section 1, Features Go
  • Throughout document, removed mention of capacitive-touch capability on I/O pinsGo
  • Updated Section 8 Specifications Go

6 Device Comparison

Table 6-1 summarizes the available family members.

Table 6-1 Device Comparison
DEVICE(1)(2) FRAM (KB) SRAM (KB) CLOCK SYSTEM LEA USS USSXT MTIF ADC12_B (Channels) Comp_E (Channels) Timer_A(3) Timer_B(4) eUSCI_A(5) eUSCI_B(6) AES BSL I/Os PACKAGE
MSP430FR6047 256 8 DCO
HFXT
LFXT
Yes Yes Yes 16 external, 2 internal 16 3, 3(7)
2, 2,2(8)
7 4 2 Yes UART 76 100 PZ (LQFP)
MSP430FR60471 256 8 DCO
HFXT
LFXT
Yes Yes Yes 16 external, 2 internal 16 3, 3(7)
2, 2,2(8)
7 4 2 Yes I2C 76 100 PZ (LQFP)
MSP430FR6037 256 8 DCO
HFXT
LFXT
Yes No Yes 16 external, 2 internal 16 3, 3(7)
2, 2,2(8)
7 4 2 Yes UART 76 100 PZ (LQFP)
MSP430FR60371 256 8 DCO
HFXT
LFXT
Yes No Yes 16 external, 2 internal 16 3, 3(7)
2, 2,2(8)
7 4 2 Yes I2C 76 100 PZ (LQFP)
MSP430FR6045 128 8 DCO
HFXT
LFXT
Yes Yes Yes 16 external, 2 internal 16 3, 3(7)
2, 2,2(8)
7 4 2 Yes UART 76 100 PZ (LQFP)
MSP430FR6035 128 8 DCO
HFXT
LFXT
Yes No Yes 16 external, 2 internal 16 3, 3(7)
2, 2,2(8)
7 4 2 Yes UART 76 100 PZ (LQFP)
(1) For the most current package and ordering information, see the Package Option Addendum in Section 12, or see the TI website at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having three capture/compare registers and PWM output generators and the second instantiation having five capture/compare registers and PWM output generators, respectively.
(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having three capture/compare registers and PWM output generators and the second instantiation having five capture/compare registers and PWM output generators, respectively.
(5) eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.
(6) eUSCI_B supports I2C with multiple slave addresses and SPI.
(7) Timers TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.
(8) Timers TA2 and TA3 provide only internal capture/compare inputs and only internal PWM outputs (if any) whereas Timer TA4 provides internal, external capture/compare inputs and internal, external PWM outputs.

 

Texas Instruments

© Copyright 1995-2025 Texas Instruments Incorporated. All rights reserved.
Submit documentation feedback | IMPORTANT NOTICE | Trademarks | Privacy policy | Cookie policy | Terms of use | Terms of sale