SLAAE21 April   2021 DAC43701 , DAC43701-Q1 , DAC53701 , DAC53701-Q1

 

  1.   Design Objective
  2.   Design Description
  3.   Design Notes
  4.   Design Simulations
    1.     Transient Simulation Results
  5.   Register Settings
  6.   Pseudo Code Example
  7.   Design Featured Devices
  8.   Design References

Design Description

This design uses a buffered voltage output smart DAC to decode two general-purpose inputs (GPIs) into a constant-frequency PWM output with four selectable duty cycle levels. This design can be expanded to increase the number of GPIs and duty cycle levels. The 8-bit DAC43701 and 10-bit DAC53701 have an integrated continuous waveform generator (CWG) that can produce square, triangular, and sawtooth waveforms. In this design, the integrated buffer acts as a comparator and a triangle waveform generated by the CWG acts as the threshold for the comparator. The DAC43701 and DAC53701 integrated buffer has an exposed feedback path via the feedback pin (FB) which acts as the voltage input to the comparator. The comparator generates a PWM output with the same frequency as the triangle wave, and a duty cycle dependent on the FB input. All register settings can be saved using the non-volatile memory (NVM) on the DAC43701 and DAC53701 meaning that the devices can be used without a processor, even after a power cycle. This circuit can be used in applications such as automotive rear lights, rear light fault indication, and fault communication in factory automation and control designs.