SFFSB36 February   2026 TMP101-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)
  7. 5Revision History

Pin Failure Mode Analysis (Pin FMA)

This section provides a failure mode analysis (FMA) for the pins of the TMP101-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

  • Pin short-circuited to ground (see Table 4-2)
  • Pin open-circuited (see Table 4-3)
  • Pin short-circuited to an adjacent pin (see Table 4-4)
  • Pin short-circuited to supply (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality.
BNo device damage, but loss of functionality.
CNo device damage, but performance degradation.
DNo device damage, no impact to functionality or performance.

Figure 4-1 shows the TMP101-Q1 pin diagram. For a detailed description of the device pins, see the Pin Configuration and Functions section in the TMP101-Q1 datasheet.

TMP101-Q1 Pin DiagramFigure 4-1 Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

  • A bypass capacitor of 0.1μF on the input voltage pin is implemented.
Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
Pin NamePin No.Description of Potential Failure EffectsFailure Effect Class
SCL1I2C communication is not possible.B
GND2There is no effect on the device. The device operates as normal.D
ALERT3The functionality of the ALERT pin is not available. The ALERT false triggers or fails to trigger, depending on the setting of the POL. If ALERT triggers continuously, the trigger can interrupt other functions of the device.B
V+4The device is not functional and is potentially damaged.A
ADD05I2C address selection is limited.B
SDA6I2C communication is not possibleB
Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin NamePin No.Description of Potential Failure EffectsFailure Effect Class
SCL1I2C communication is not possible.B
GND2The functionality of the device is undetermined.B
ALERT3The functionality of the ALERT pin is not available.B
V+4The functionality of the device is undetermined.B
ADD05I2C address selection is limited.B
SDA6I2C communication is not possible.B
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin NamePin No.Shorted toDescription of Potential Failure EffectsFailure Effect Class
SCL1GNDI2C communication is not possible.B
GND2ALERTThe functionality of the ALERT pin is not available. The ALERT false triggers or fails to trigger, depending on the setting of the POL. If ALERT triggers continuously, the trigger can interrupt other functions of the device.B
ALERT3V+The functionality of the ALERT pin is not available. The ALERT false triggers or fails to trigger, depending on the setting of the POL. If ALERT triggers continuously, the trigger can interrupt other functions of the device.B
V+4ADD0I2C address selection is limited.B
ADD05SDAI2C communication is not possible.B
SDA6SCLI2C communication is not possible.B
Table 4-5 Pin FMA for Device Pins Short-Circuited to Supply
Pin NamePin No.Description of Potential Failure EffectsFailure Effect Class
SCL1I2C communication is not possible.B
GND2The device is not functional and is potentially damaged.A
ALERT3The functionality of the ALERT pin is not available. The ALERT false triggers or fails to trigger, depending on the setting of the POL. If ALERT triggers continuously, the trigger can interrupt other functions of the device.B
V+4There is no effect on the device. The device operates as normal.D
ADD05I2C address selection is limited.B
SDA6I2C communication is not possible.B