SFFSAD5 July   2025 TPS7B87-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1 TO-252 Package
    2. 2.2 HSOIC Package
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 TO-252 Package
    2. 4.2 HSOIC Package B Version
  7. 5Revision History

4.2 HSOIC Package B Version

Figure 4-2 shows the TPS7B87-Q1 pin diagram for the HSOIC package B version with PG. For a detailed description of the device pins, see the Pin Configuration and Functions section in the TPS7B87-Q1 data sheet.

TPS7B87-Q1 Pin Diagram (HSOIC Package B Version With PG) Figure 4-2 Pin Diagram
(HSOIC Package B Version With PG)
Table 4-6 Pin FMA for Device Pins Short-Circuited to Ground
Pin Name Pin No. Description of Potential Failure Effects Failure Effect Class
OUT 1 Regulation is not possible, the device operates at current limit. The device can cycle in and out of thermal shutdown. B
NC 2 No effect. Normal operation. B
DELAY 3 Ground current is permanently increased. C
NC 4 No effect. Normal operation. D
GND 5 No effect. Normal operation. D
PG 6 Power-good never asserts when the output voltage is at target, thus, potentially effecting power sequencing. B
NC 7 No effect. Normal operation. D
IN 8 Power is not supplied to the device. System performance depends on upstream current limiting. B
Table 4-7 Pin FMA for Device Pins Open-Circuited
Pin Name Pin No. Description of Potential Failure Effects Failure Effect Class
OUT 1 The device output is disconnected from the load. B
NC 2 No effect. Normal operation. D
DELAY 3 The power-good delay is set to the minimum delay time, t(DLY_FIX). C
NC 4 No effect. Normal operation. D
GND 5 There is no current loop for the supply voltage. The device is not operational and does not regulate. B
PG 6 The power-good signal is not accessible. Power sequencing can be effected. B
NC 7 No effect. Normal operation. D
IN 8 Power is not supplied to the device, resulting in no output voltage. B
Table 4-8 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin Name Pin No. Shorted to Description of Potential Failure Effects Failure Effect Class
OUT 1 2 - NC No effect. Normal operation. D
NC 2 3 - DELAY No effect. Normal operation. D
DELAY 3 4 - NC No effect. Normal operation. D
GND 5 6 - PG Power-good functionality cannot operate correctly, always low. B
PG 6 7 - NC No effect. Normal operation. D
NC 7 8 - IN No effect. Normal operation. D
Table 4-9 Pin FMA for Device Pins Short-Circuited to VIN
Pin Name Pin No. Description of Potential Failure Effects Failure Effect Class
OUT 1 Output held at VIN, regulation is not possible. Damage is possible if the absolute maximum rating is exceeded (20V max). A
NC 2 No effect. Normal operation. D
DELAY 3 PG can incorrectly assert when the output voltage is not at target. The pin absolute maximum rating (6V max) can be exceeded and the pin can be damaged. A
B
NC 4 No effect. Normal operation. D
GND 5 Power is not supplied to the device. System performance depends on upstream current limiting. B
PG 6 Power-good functionality cannot operate correctly. PG can be damaged if the absolute maximum rating (20V) is violated. A
B
NC 7 No effect. Normal operation. D
IN 8 No effect. Normal operation. D