SFFSAB6 March 2025 TPSI3050M
4 Pin Failure Mode Analysis (Pin FMA)
This section provides a failure mode analysis (FMA) for the pins of the TPSI3050M. The failure modes covered in this document include the typical pin-by-pin failure scenarios for three-wire mode and two-wire mode:
- Pin short-circuited to VSSP or VSSS (see Table 4-2 and Table 4-6)
- Pin open-circuited (see Table 4-3 and Table 4-7)
- Pin short-circuited to an adjacent pin (see Table 4-4 and Table 4-8)
- Pin short-circuited to VDDP (see Table 4-5 and Table 4-9)
Table 4-2 through Table 4-9 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-2.
Table 4-1 TI Classification of Failure
Effects
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality. |
| B | No device damage, but loss of functionality. |
| C | No device damage, but performance degradation. |
| D | No device damage, no impact to functionality or performance. |
Figure 4-1 shows the TPSI3050M pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the TPSI3050M data sheet.
Figure 4-1 Pin DiagramThe TPSI3050M is normally operated in one of two modes of operation for a given application: three-wire mode or two-wire mode. The pin FMA was performed individually for each of these modes of operation in the following sections.
Three-Wire Mode
Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:
- Device configured and operating in three-wire mode
- Device in normal operation prior to any open or short condition being applied to the respective pin
- EN set to a static logic low or high (VDRV asserted low or high respectively)
- Opens or shorts occur relative to primary and secondary sides of the device and is a static event
Table 4-2 Three-Wire Mode: Pin FMA for
Device Pins Short-Circuited to VSSP or VSSS
| Pin Name | Pin No. | Ground | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|---|
| EN | 1 | VSSP | VDRV asserts low. | B |
| PXFR | 2 | VSSP | Subsequent power cycles result in RPXFR selection to 7.32kΩ, which can result in longer start-up and recovery times if a different RPXFR selection from 7.32kΩ is used in the application. | C |
| VDDP | 3 | VSSP | No power transfer. VDDH and VDDM rails collapse. VDRV asserts low with active clamp enabled. If EN static is high, additional leakage current into the EN pin is observed on the order of 25mA. | B |
| VDRV | 8 | VSSS | If VDRV is high, VDDH and VDDM rails collapse. VDRV asserts low with an active clamp enabled. If VDRV is low, no effect. | B |
| VDDH | 7 | VSSS | VDDH and VDDM rails collapse. VDRV asserts low with an active clamp enabled. | B |
| VDDM | 6 | VSSS | VDDH and VDDM rails collapse. VDRV asserts low with an active clamp enabled. | B |
Table 4-3 Three-Wire Mode: Pin FMA for
Device Pins Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| EN | 1 | VDRV asserts low. The EN pin has an internal resistive pulldown to VSSP. | B |
| PXFR | 2 | Subsequent power cycles result in RPXFR selection to 7.32kΩ, which can result in longer start-up and recovery times if a different RPXFR selection from 7.32kΩ is used in the application. | C |
| VDDP | 3 | No power transfer. VDDH and VDDM rails collapse. VDRV asserts low with an active clamp enabled. | B |
| VSSP | 4 | No power transfer. VDDH and VDDM rails collapse. VDRV asserts low with an active clamp enabled. | B |
| VDRV | 8 | No drive to the external switch. The external switch gate control can float dependent upon application circuitry. | B |
| VDDH | 7 | VDDH can collapse under loading or switching events. | B |
| VDDM | 6 | VDDH and VDDM can collapse under loading or switching events. | B |
| VSSS | 5 | Normal power transfer. VDDH and VDDM rails remain charged. VDRV follows the state of EN logic level. Since VSSS is a floating ground, VSSS cannot drive the external switch. | B |
Table 4-4 Three-Wire Mode: Pin FMA for
Device Pins Short-Circuited to Adjacent Pin
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|---|
| VDDH | 7 | VDDM | VDDH and VDDM rails collapse. VDRV asserts low with an active clamp enabled. | B |
| VDRV | 8 | VDDH | If VDRV is low, VDDH and VDDM rails collapse. VDRV remains low with an active clamp enabled. If VDRV is high, no effect. | B |
| EN | 1 | PXFR | Subsequent power cycles result in RPXFR selection to 7.32kΩ, which can result in longer start-up and recovery times if a different RPXFR selection from 7.32kΩ is used in the application. | C |
Table 4-5 Three-Wire Mode: Pin FMA for
Device Pins Short-Circuited to
VDDP
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| EN | 1 | VDRV asserts high. | B |
| PXFR | 2 | Subsequent power cycles result in RPXFR selection to 7.32kΩ, which can result in longer start-up and recovery times if a different RPXFR selection from 7.32kΩ is used in the application. | C |
Two-Wire Mode
Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:
- Device configured and operating in two-wire mode
- Device in normal operation prior to any open or short condition being applied to the respective pin
- EN set to a static high (VDRV asserted high)
- Opens or shorts occur relative to primary and secondary sides of the device and is a static event
Table 4-6 Two-Wire Mode: Pin FMA for
Device Pins Short-Circuited to VSSP or VSSS
| Pin Name | Pin No. | Ground | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|---|
| EN | 1 | VSSP | No power transfer. VDDH and VDDM rails collapse. VDRV asserts low with an active clamp enabled. | B |
| PXFR | 2 | VSSP | Subsequent power cycles result in RPXFR selection to 7.32kΩ, which can result in longer start-up and recovery times if a different RPXFR selection from 7.32kΩ is used in the application. | C |
| VDDP | 3 | VSSP | No power transfer. VDDH and VDDM rails collapse. VDRV asserts low with an active clamp enabled. Additional leakage current into the EN pin is observed on the order of 25mA. | B |
| VDRV | 8 | VSSS | VDDH and VDDM rails collapse. VDRV asserts low with an active clamp enabled. | B |
| VDDH | 7 | VSSS | VDDH and VDDM rails collapse. VDRV asserts low with an active clamp enabled. | B |
| VDDM | 6 | VSSS | VDDH and VDDM rails collapse. VDRV asserts low with an active clamp enabled. | B |
Table 4-7 Two-Wire Mode: Pin FMA for Device Pins Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| EN | 1 | No power transfer. VDDH and VDDM rails collapse. VDRV asserts low with an active clamp enabled. The EN pin has an internal resistive pulldown to VSSP. | B |
| PXFR | 2 | Subsequent power cycles result in RPXFR selection to 7.32kΩ, which can result in longer start-up and recovery times if a different RPXFR selection from 7.32kΩ is used in the application. | C |
| VDDP | 3 | No power transfer. VDDH and VDDM rails collapse. VDRV asserts low with an active clamp enabled. | B |
| VSSP | 4 | No power transfer. VDDH and VDDM rails collapse. VDRV asserts low with an active clamp enabled. | B |
| VDRV | 8 | No drive to the external switch. The external switch gate control can float dependent upon application circuitry. | B |
| VDDH | 7 | VDDH can collapse under loading or switching events. | B |
| VDDM | 6 | VDDH and VDDM can collapse under loading or switching events. | B |
| VSSS | 5 | Normal power transfer. VDDH and VDDM rails remain charged. VDRV follows the state of EN logic level. Since VSSS is a floating ground, VSSS cannot drive the external switch. | B |
Table 4-8 Two-Wire Mode: Pin FMA for Device Pins Short-Circuited to Adjacent
Pin
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|---|
| VDDH | 7 | VDDM | VDDH and VDDM rails collapse. VDRV asserts low with an active clamp enabled. | B |
| VDRV | 8 | VDDH | VDRV remains high. | B |
| EN | 1 | PXFR | Subsequent power cycles result in RPXFR selection to 7.32kΩ, which can result in longer start-up and recovery times if a different RPXFR selection from 7.32kΩ is used in the application. | C |
Table 4-9 Two-Wire Mode: Pin FMA for Device Pins Short-Circuited to
VDDP
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| EN | 1 | If EN voltage exceeds the absolute maximum of VDDP, potential damage of device can occur. | A |
| PXFR | 2 | Subsequent power cycles result in RPXFR selection to 7.32kΩ, which can result in longer start-up and recovery times if a different RPXFR selection from 7.32kΩ is used in the application. | C |