SFFS988 September 2024 LM5109B-Q1

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a failure mode analysis (FMA) for the pins of the LM5109B-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Pin short-circuited to ground (see Table 4-2)
Pin open-circuited (see Table 4-3)
Pin short-circuited to an adjacent pin (see Table 4-4)
Pin short-circuited to supply (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects

Class	Failure Effects
A	Potential device damage that affects functionality.
B	No device damage, but loss of functionality.
C	No device damage, but performance degradation.
D	No device damage, no impact to functionality or performance.

Figure 4-1 shows the LM5109B-Q1 pin diagram. For a detailed description of the device pins, see the Pin Configuration and Functions section in the LM5109B-Q1 data sheet.

Figure 4-1 Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

Short between VDD and HB is not considered.
Short between VSS and LO is not considered.

Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground

Pin Name	Pin No.	Description of Potential Failure Effects	Failure Effect Class
VDD	1	The device is not powered.	C
HI	2	HO is pulled low (sinking is on). HI is stuck low.	C
LI	3	LO is pulled low (sinking is on). LI is stuck low.	C
VSS	4	No impact. Short to same potential.	D
LO	5	LO is stuck low.	A
HS	6	HS is stuck low. Power FET short circuit HV and HS when HI = H is commanded.	D
HO	7	HO is stuck low. Device damage is possible when HI = H is commanded.	A
HB	8	HO is stuck low. Boot diode damage is possible.	D

Table 4-3 Pin FMA for Device Pins Open-Circuited

Pin Name	Pin No.	Description of Potential Failure Effects	Failure Effect Class
VDD	1	The device is not powered.	D
HI	2	HI is pulled down by the internal pulldown resistor. HO is pulled down (sinking is on).	C
LI	3	LI is pulled down by the internal pulldown resistor. LO is pulled down (sinking is on).	C
VSS	4	HI and LI float to VDD level. HO and LO float to VDD level.	C
LO	5	LO is disconnected from the gate of the power FET.	D
HS	6	Low side output has no supply. LO is pulled down (sinking is on).	C
HO	7	HO is disconnected from the gate of the power FET.	D
HB	8	High-side output has no supply. HO is pulled down (sinking is on).	C

Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin

Pin Name	Pin No.	Shorted to	Description of Potential Failure Effects	Failure Effect Class
VDD	1	HI	HI is stuck high. HO is pulled up (sourcing is on).	C
HI	2	LI	HI and LI are undefined.	C
LI	3	VSS	LI is stuck low.	C
VSS	4	N/A	N/A	N/A
LO	5	HS	LO is in an overvoltage condition and potentially exposed to VIN level when HI = H is commanded.	A
HS	6	HO	High-side HO output level is 0 (HO-HS). High-side power FET is off (VGS is stuck low).	A
HO	7	HB	HO is stuck high. HO is pulled up to VDD level. Power FET damage is possible when LI = H is commanded.	A
HB	8	N/A	N/A	N/A

Table 4-5 Pin FMA for Device Pins Short-Circuited to VDD

Pin Name	Pin No.	Description of Potential Failure Effects	Failure Effect Class
VDD	1	No impact. Short to same potential.	D
HI	2	HI is stuck high. HO is pulled up (sourcing is on).	C
LI	3	LI is stuck high. LO is pulled up (sourcing is on).	C
VSS	4	VDD short to VSS The device is not powered.	C
LO	5	LO is stuck high and device damage is possible. Power FET damage is possible when HI = H is commanded.	A
HS	6	HO (and HS) is pulled to VDD level.	C
HO	7	HO is stuck high and device damage is possible. Power FET damage is possible when LI = H is commanded.	A
HB	8	HO output voltage (sourcing on) is lower than the specified range.	C