SFFS948 May 2025 MSPM0L1227-Q1 , MSPM0L1228-Q1 , MSPM0L2227-Q1 , MSPM0L2228-Q1
The MSPM0 MCUs include a low-power, high-performance SRAM with zero wait state access across the supported CPU frequency range of the device. The MSPM0 MCUs also provide up to 32KB of ECC protected SRAM with hardware parity. SRAM can be used for storing volatile information, such as, the call stack, heap, global data, and code. The SRAM content is fully retained in RUN, SLEEP, STOP, and STANDBY modes and is lost in shutdown mode. A write-execute, mutual-exclusion mechanism is provided to allow the application to partition the SRAM into two sections:
The RX partition occupies the upper portion of the SRAM address space. Write protection is useful when placing executable code into SRAM, as the write protection provides a level of protection against unintentional overwrites of code by either the CPU or DMA. Placing code in SRAM can improve performance of critical loops by enabling a zero wait state operation and lower power consumption.
The following tests must be applied for the targeted ASIL as functional safety mechanisms for this module (to provide diagnostic coverage on a specific function):
| Safety Mechanism | Description | Faults | Failure Modes |
|---|---|---|
| SYSMEM1 | Software read of memory DMA | Targeted toward the DMA bus decoder in the SRAM controller and the arbitration logic. |
| SYSMEM2 | Software read of memory CPU | Targeted toward the CPU bus decoder in the SRAM controller and the arbitration logic. |
| SYSMEM7 | RAM ECC | Targeted toward the faults in SRAM. |
| SYSMEM9 | RAM software test | Targeted towards multipoint latent faults in SRAM. |
| SYSMEM8 (latent fault coverage) | ECC logic test | This is a test of diagnostic. This test is used to test the function of the ECC checker logic. |
| WDT | Windowed watchdog event | Targeted toward arbitration logic. Any fault which leads to a CPU bus hang can be covered by this mechanism. |