SFFS756 November   2023 SN74HCS20-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1 D and PW Packages
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 D and PW Packages
  7. 5Revision History

4.1 D and PW Packages

Pin Diagram (D and PW) Packages shows the SN74HCS20-Q1 pin diagram for the D and PW packages. For a detailed description of the device pins and their corresponding pin type, please refer to the Pin Configuration and Functions section in the SN74HCS20-Q1 data sheet.

GUID-98E80CBE-FD37-4594-A453-9FFE4CCC20BF-low.gifFigure 4-1 Pin Diagram (D and PW) Packages
Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
NC 3, 11 Normal operation. D
A, B, C, D1, 2, 4, 5, 9, 10, 12, 13Input pin is forced to the low logic state. See Device Function Table in the device data sheet for details of how the failure affects functionality.B
GND7Normal operation.D
Y6, 8Can cause excessive output current; output remains in the low output state independent of input states.A
VCC14Device is not powered. System level damage can occur in this scenario.B
Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
NC 3, 11 Normal operation. D
A, B, C, D1, 2, 4, 5, 9, 10, 12, 13Pin is floating, can change output state and cause excessive current from VCC to GND. See Implications of Slow or Floating CMOS Inputs.A
GND7Device is not powered.B
Y6, 8Normal operation.D
VCC14Device is not powered.B
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin NamePin No.Shorted toDescription of Potential Failure Effect(s)Failure Effect Class
NC 3, 11 A, B, C, D, Y, VCC, GND, Thermal Pad Normal operation. D
A, B, C, D1, 2, 4, 5, 9, 10, 12, 13A, B, C, DTwo inputs shorted together can cause a loss of functionality or damage to the device. Damage to the device can occur when the input voltage (VI) is driven such that VIL < VI < VIH.A
A, B, C, D1, 2, 4, 5, 9, 10, 12, 13YCan cause loss of functionality or damage to the device. Damage to the device can occur due to feedback oscillation causing excessive current consumption.A
A, B, C, D1, 2, 4, 5, 9, 10, 12, 13GNDInput pin is forced to the low logic state. See Device Function Table in the device data sheet for details of how the failure affects functionality.B
A, B, C, D1, 2, 4, 5, 9, 10, 12, 13Thermal PadInput pin is forced to the low logic state. See Device Function Table in the device data sheet for details of how the failure affects functionality.

B

A, B, C, D1, 2, 4, 5, 9, 10, 12, 13VCCInput pin is forced to the high logic state. See Device Function Table in the device data sheet for details of how the failure affects functionality.B
Y6, 8GNDCan cause excessive output current; output remains in the low output state independent of input states.A
Y6, 8Thermal PadCan cause excessive output current; output remains in the low output state independent of input states.

A

Y6, 8VCCCan cause excessive output current; output remains in the high output state independent of input states.A
Table 4-5 Pin FMA for Device Pins Short-Circuited to VCC
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
NC 3, 11 Normal operation. D
A, B, C, D1, 2, 4, 5, 9, 10, 12, 13Input pin is forced to the high logic state. See Device Function Table in the device data sheet for details of how the failure affects functionality.B
GND7Device is not powered. System level damage can occur in this scenario.B
Y6, 8Can cause excessive output current; output remains in the high output state independent of input states.A
VCC14Normal operation.D