SFFS685 March   2025 CDC6C-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1 VSON (DLN) Package
    2. 2.2 VSON (DLF) Package
    3. 2.3 VSON (DLR) Package
    4. 2.4 VSON (DLY) Package
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)
  7. 5Revision History

3 Failure Mode Distribution (FMD)

The failure mode distribution estimation for the CDC6C-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity, and from best engineering judgment.

The failure modes listed in this section reflect random failure events and do not include failures resulting from misuse or overstress.

Table 3-1 Die Failure Modes and Distribution
Die Failure Modes Failure Mode Distribution (%)
Performance degradation of output clock 40
Incorrect output frequency, poor timing accuracy 30
No output clock 30