SFFS612 May 2025 TPS748A-Q1
4.1 VSON Package
Figure 4-1 shows the TPS748A-Q1 pin diagram for the VSON package. For a detailed description of the device pins, see the Pin Configuration and Functions section in the TPS748A-Q1 data sheet.
Figure 4-1 Pin Diagram (VSON Package)Table 4-2 Pin FMA for Device Pins
Short-Circuited to Ground
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| IN | 1 | Device does not turn on. No damage to device. | B |
| IN | 2 | Device does not turn on. No damage to device. | B |
| PG | 3 | No damage to device. PG functionality does not work. No impact on remaining functionality. | B |
| BIAS | 4 | No damage to device. Since band gap and control circuits do not power up, the output voltage is not regulated and remains low at 0V. | B |
| EN | 5 | Device does not turn on. No damage to device. | B |
| GND | 6 | No Impact. Normal operation. | D |
| SS | 7 | Quiescent current increases. Device output remains at 0V. No damage to device. | B |
| FB | 8 | Loss of functionality, device does not regulate. Output voltage tracks input voltage and equals VIN minus the dropout. No damage to device. | B |
| OUT | 9 | Device hits a current limit state. If the power dissipation is significant, the device hits a thermal shutdown state, and can continue to cycle between the two states. Continuously running the device above the rated current degrades device reliability. | A |
| OUT | 10 | Same as pin 9. | A |
Table 4-3 Pin FMA for Device Pins
Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| IN | 1 | Normal operation. Power supply is still connected to the remaining IN pin (2). There is a small risk that the bond wire connecting to the remaining IN pin can fuse under heavily loaded conditions. | A |
| D | |||
| IN | 2 | Same as pin 1. | A |
| D | |||
| PG | 3 | No damage to device. PG functionality does not work. No impact on remaining functionality. | B |
| BIAS | 4 | No damage to device. Since band gap and control circuits do not power up, the output voltage is not regulated and remains low at 0V. | B |
| EN | 5 | Since the voltage floats to an indeterminate value, the device can disable. | B |
| GND | 6 | With the reference pin floating, the voltages at the remaining pins are also floating and the device is not functional. There is a risk of violating the absolute maximum ratings. | A |
| B | |||
| SS | 7 | No impact. Normal operation. Start-up time defaults to 200μs, approximately. | D |
| FB | 8 | Loss of functionality. The output pin voltage is not regulated and remains in an indeterminate state. | B |
| OUT | 9 | No impact. Normal operation. Load is still connected to the remaining OUT pin (10). There is a small risk that the bond wire connecting to the remaining OUT pin can fuse under heavily loaded conditions. | A |
| D | |||
| OUT | 10 | Same as pin 9. | A |
| D |
Table 4-4 Pin FMA for Device Pins
Short-Circuited to Adjacent Pin
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|---|
| IN | 1 | IN | No impact. Normal operation. | D |
| IN | 2 | PG | Very high risk of damage to the PG pin and device, resulting from excess current drawn when the PG open drain becomes low impedance. | A |
| PG | 3 | BIAS | Very high risk of damage to the PG pin and device, resulting from excess current drawn when the PG open drain becomes low impedance. | A |
| BIAS | 4 | EN | Device remains ON regardless of the enable signal value. | B |
| EN | 5 | GND | Device remains OFF regardless of the enable signal value. | B |
| GND | 6 | SS | Quiescent current increases. Device output remains at 0V. No damage to device. | B |
| SS | 7 | FB | The error amplifier output rails to either one of the supplies, and the LDO output is either at 0V or tracks VIN and equals VIN – dropout. | B |
| FB | 8 | OUT | VOUT is set to VFB = 0.8V. | B |
| OUT | 9 | OUT | No impact. Normal operation. | D |
| OUT | 10 | IN | Output voltage is not regulated and equals VIN. | B |
Table 4-5 Pin FMA for Device Pins
Short-Circuited to
Supply
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| IN | 1 | No impact. Normal operation. | D |
| IN | 2 | No impact. Normal operation. | D |
| PG | 3 | Very high risk of damage to the PG pin and device, resulting from excess current drawn when the PG open drain becomes low impedance. | A |
| BIAS | 4 | Normal operation is only established if there is sufficient dropout (VIN ≥ VOUT + VDO, where VDO = IOUT × (1.6 / 1.5) and VIN (VIN ≥ 2.7V) are provided. Device does not turn on for lower values of VIN, and VOUT remains at 0V. | B |
| EN | 5 | Device remains ON regardless of the enable signal value. | B |
| GND | 6 | Device does not turn on. | B |
| SS | 7 | The LDO output pin voltage is not regulated and tracks VIN. VOUT equals VIN – dropout. | B |
| FB | 8 | The LDO output pin voltage is not regulated and equals VIN (under no-load conditions). | B |
| OUT | 9 | Device is not functional, the output voltage is not regulated and equals VIN. | B |
| OUT | 10 | Same as pin 9. | B |