SFFS608 june   2023 TPS3435 , TPS3435-Q1 , TPS3436-Q1 , TPS35 , TPS35-Q1 , TPS36-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)

Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the TPS3435, TPS3436, TPS35, and TPS36. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

  • Pin short-circuited to Ground (see Table 4-2)
  • Pin open-circuited (see Table 4-3)
  • Pin short-circuited to an adjacent pin (see Table 4-3)
  • Pin short-circuited to supply (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality
BNo device damage, but loss of functionality
CNo device damage, but performance degradation
DNo device damage, no impact to functionality or performance

Figure 4-1 and Figure 4-2 show the TPS3435, TPS3436, TPS35, and TPS36 pin diagrams. For a detailed description of the device pins please refer to TPS3435, TPS3436, TPS35, or TPS36 in the Pin Configuration and Functions section of the data sheet.

GUID-20210630-CA0I-QB3N-JCB7-3CZPPD31LPJX-low.svgFigure 4-1 Pin Configuration Option C
DDF Package,8-Pin SOT-23,
TPS35 and TPS36 Top View
GUID-20210630-CA0I-RFBF-MFKM-1QBWRWNFXRFM-low.svgFigure 4-2 Pin Configuration Option C
DDF Package,8-Pin SOT-23,
TPS3435 and TPS3436 Top View

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

  • Output reset Pullup Resistor (RPULLUP) = 10 kΩ, Output reset pullup voltage (VPULLUP = 5.5 V, output reset load (CLOAD) = 10 pF.
  • Tables valid over the operating free-air temperature range of – 40°C to 125°C, unless otherwise noted.
  • Typical values are at TA = 25°C, VDD = 6.0 V unless stated otherwise.
Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
PIN NAMEPIN NO.DESCRIPTION OF POTENTIAL FAILURE EFFECT(S)FAILURE EFFECT CLASS
SET01

Unexpected behavior if application needs SET0 = 1.

B

MR

2RESET/WDO is asserted.

B

WDI

3

Constant WD timeout faults.

B

GND

4

Expected operating condition.

D

SET15

Unexpected behavior if application needs SET1 = 1.

B

WD-EN

6Leads to large indeterminate voltage levels. This causes large currents that can damage the device. The output behavior is not deterministic.A
WDO / RESET(Open Drain)7

WDO / RESET constantly asserted; some additional current can flow through pullup resistor.

B

WDO / RESET(Push Pull)7Functionality lost and can cause permanent damage.

A

VDD8Device non-operational.

B

Table 4-3 Pin FMA for Device Pins Open-Circuited
PIN NAMEPIN NO.DESCRIPTION OF POTENTIAL FAILURE EFFECT(S)FAILURE EFFECT CLASS
SET01

Leads to large indeterminate voltage levels. This causes large currents that can damage the device. The output behavior is not deterministic.

A

MR

2Device can not pass MR to RESET. B

WDI

3Nothing happens until error condition, then reset delay is 2 mS.C

GND

4Device is non-operational.B
SET15Leads to large indeterminate voltage levels. This causes large currents that can damage the device. The output behavior is not deterministic.A

WD-EN

6Nothing happens until error condition or power cycle, then WD is disabled.B
WDO / RESET(Open Drain)7Constant high, no WDO/RESET functionality.B
WDO / RESET(Push Pull)7High impedance output, no WDO/RESET functionality.B
VDD8Device is non-operational.

B

Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
PIN NAMEPIN NO.SHORTED TODESCRIPTION OF POTENTIAL FAILURE EFFECT(S)FAILURE EFFECT CLASS
SET01

MR

High current at a system level can flow to the device driving MR or SET0.

B

MR

2

WDI

High current at a system level can flow to the device driving MR or WDI.

B

WDI

3

GND

Constant WD timeout faults.

B

GND

4SET1

Unexpected behavior if application needs SET1 = 1.

B

SET15

WD-EN

SET1 toggles with WD-EN.

B

WD-EN

6WDO / RESET(Open Drain)

High current can flow from WD-EN or WDO / RESET based on the pullup resistor value.

B

WD-EN

6WDO / RESET(Push Pull)Can cause permanent damage.

A

WDO / RESET(Open Drain)7VDD

Large current can flow into WDO/RESET when in error condition. This can cause permanant damage.

A

WDO / RESET(Push Pull)7VDD

Can cause permanent damage.

A

VDD

8SET0

Unexpected behavior if application needs SET0 = 0.

B

Table 4-5 Pin FMA for Device Pins Short-Circuited to VDD
PIN NAMEPIN NO.DESCRIPTION OF POTENTIAL FAILURE EFFECT(S)FAILURE EFFECT CLASS
SET01Unexpected behavior if application needs SET0 = 0.

B

MR

2

High current can flow into the device driving MR.

B

WDI

3

Constant WD timeout faults.

B

GND

4

Device is non-operational.

B

SET15Unexpected behavior if application needs SET1 = 0.

B

WD-EN

6Watchdog is always enabled, loss of WD-disable functionality.B
WDO / RESET(Open Drain)7Large current can flow into WDO/RESET when in error condition. This can cause permanant damage.A
WDO / RESET(Push Pull)7Can cause permanent damage.

A

VDD8Normal operation.

D