SFFS535A September 2022 – March 2024 TPSM33615 , TPSM33625

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a failure mode analysis (FMA) for the pins of the TPSM33625, TPSM33615. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Pin short-circuited to ground (see Table 4-2)
Pin open-circuited (see Table 4-3)
Pin short-circuited to an adjacent pin (see Table 4-4)
Pin short-circuited to supply (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects

Class	Failure Effects
A	Potential device damage that affects functionality.
B	No device damage, but loss of functionality.
C	No device damage, but performance degradation.
D	No device damage, no impact to functionality or performance.

Figure 4-1 shows the TPSM33625, TPSM33615 pin diagram. For a detailed description of the device pins, see the Pin Configuration and Functions section in the TPSM33625, TPSM33615 data sheet.

Figure 4-1 Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

The product data sheet application circuit is followed.

Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground

Pin Name	Pin No.	Description of Potential Failure Effects	Failure Effect Class
RT	11	Switching Frequency is 2.2MHz	D
PGOOD	1	When not in use, can be left open, grounded.	D
EN/UVLO	2	VOUT = 0V; part is disabled	B
VIN	3	VOUT = 0V	B
SW	5 and 6	Device damage.	A
BOOT	7	VOUT = 0, HS does not turn on	B
VCC	8	VOUT = 0V	B
FB	9	VOUT = 0V	B
GND	10	VOUT normal	D
VOUT	4	Goes in to hiccup; short-circuit operation	B

Table 4-3 Pin FMA for Device Pins Open-Circuited

Pin Name	Pin No.	Description of Potential Failure Effects	Failure Effect Class
RT	11	If its RT part, frequency is not defined. If it is a MODE/SYNC part, then part can go back and forth between FPWM/PFM. Part is up, part functional.	C
PGOOD	1	When not in use, can be left open, grounded.	D
EN/UVLO	2	Pin cannot be left floating	B
VIN	3	VOUT = 0V	B
SW	5 and 6	Normal operation	D
BOOT	7	Normal operation	D
VCC	8	VCC output is unstable, can increase above 5.5V	A
FB	9	VOUT = 0V. Do not float this pin.	C
GND	10	Vout can be abnormal, as reference voltage is not fixed	C
VOUT	4	Normal operation	B

Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin

Pin Name	Pin No.	Shorted to	Description of Potential Failure Effects	Failure Effect Class
RT	11	PGOOD	If PGOOD is high, and < 5.5V Fsw = 1MHz; If PGOOD is low, Fsw = 2.2 MHz . PGOOD abs max being 20V, RT ESD damages if PG goes to 20V.	A
PGOOD	1	EN/UVLO	If EN > 20V, it damages devices connected to PGOOD pin.	A
EN/UVLO	2	VIN	VOUT normal	D
VIN	3	SW	If VIN > 16V, damage occurs	A
SW	5 and 6	BOOT	VOUT = 0V, HS does not turn on, no Cboot	B
BOOT	7	VCC	Damage occurs, break VCC pin	A
VCC	8	FB	Can be nonfunctional, no damage occurs	B
FB	9	GND	VOUT = 0V (for fixed option), switches at max duty cycle for ADJ option	B
GND	10	RT	VOUT normal if RT/MODE/SYNC pin is low, otherwise not functional.	D
Vout	4	SW	Damage occurs	A

Table 4-5 Pin FMA for Device Pins Short-Circuited to supply

Pin Name	Pin No.	Description of Potential Failure Effects	Failure Effect Class
RT	11	If Vin > 5.5V, damage occurs. If Vin < 5.5V, switching frequency is 1MHz	A
PGOOD	1	If VIN > 20V, it damages PGOOD	A
EN/UVLO	2	VOUT normal	D
VIN	3	VOUT normal	D
SW	5 and 6	Device damage	A
BOOT	7	Damage occurs, BOOT ESD clamp is damaged	A
VCC	8	If Vin > 5.5, damage occurs	A
FB	9	If VIN > 20V, damage occurs	A
GND	10	VOUT = 0V	A
VOUT	4	Damage occurs if VIN > 16V	A