SFFS392B September 2022 – July 2025 TMP1827
4.1 WSON-8 Package
Figure 4-1 shows the TMP1827 pin diagram for the WSON-8 package. For a detailed description of the device pins, see the Pin Configuration and Functions section in the TMP1827 data sheet.
Figure 4-1 Pin Diagram (WSON-8 Package)Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| ADDR | 3 | Limited address selection. Application must revert to 64 bit addressing mode. | C |
| If ADDR selection is not being used, then no effect. | D | ||
| GND | 4 | No effect. Normal operation. | D |
| IO0 | 6 | If I/O is used for controlling an external component, functionality is lost. | B |
| If I/O is not being used, then no effect. | D | ||
| IO1 | 7 | If I/O is used for controlling an external component, functionality is lost. | B |
| If I/O is not being used, then no effect. | D | ||
| IO2 | 8 | If I/O is used for controlling an external component, functionality is lost. | B |
| If I/O is not being used, then no effect. | D | ||
| IO3 | 5 | If I/O is used for controlling an external component, functionality is lost. | B |
| If I/O is not being used, then no effect. | D | ||
| SDQ | 2 | No communication. | B |
| VDD | 1 | Device is in bus powered mode. | C |
Table 4-3 Pin FMA for Device Pins Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| ADDR | 3 | Limited address selection. Application must revert to 64 bit addressing mode. | C |
| GND | 4 | When floating, possible latch-up. | B |
| IO0 | 6 | If I/O is used for controlling an external component, functionality is lost. | B |
| If I/O is not being used, then no effect. | D | ||
| IO1 | 7 | If I/O is used for controlling an external component, functionality is lost. | B |
| If I/O is not being used, then no effect. | D | ||
| IO2 | 8 | If I/O is used for controlling an external component, functionality is lost. | B |
| If I/O is not being used, then no effect. | D | ||
| IO3 | 5 | If I/O is used for controlling an external component, functionality is lost. | B |
| If I/O is not being used, then no effect. | D | ||
| SDQ | 2 | No communication. | B |
| VDD | 1 | Device is in bus powered mode. | C |
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|---|
| ADDR | 3 | SDQ | The absolute maximum for the ADDR pin is 1.65V. If shorted to SDQ, and SDQ is pulled to 5.5V, can cause leakage currents to increase and damage the device during ADDR detection. | A |
| GND | 4 | ADDR | If ADDR is shorted to GND, then address selection is limited. Application must revert to 64 bit addressing mode. | C |
| GND is shorted to ADDR pin, has no affect during normal operation. | D | |||
| IO0 | 6 | IO1 | If I/O is used for controlling an external component, functionality is lost. | B |
| If I/O is not being used, then no effect. | D | |||
| IO0 | 6 | IO3 | If I/O is used for controlling an external component, functionality is lost. | B |
| If I/O is not being used, then no effect. | D | |||
| IO1 | 7 | IO2 | If I/O is used for controlling an external component, functionality is lost. | B |
| If I/O is not being used, then no effect. | D | |||
| IO1 | 7 | IO0 | If I/O is used for controlling an external component, functionality is lost. | B |
| If I/O is not being used, then no effect. | D | |||
| IO2 | 8 | IO1 | If I/O is used for controlling an external component, functionality is lost. | B |
| If I/O is not being used, then no effect. | D | |||
| IO3 | 5 | IO0 | If I/O is used for controlling an external component, functionality is lost. | B |
| If I/O is not being used, then no effect. | D | |||
| SDQ | 2 | VDD | Loss of functionality. Communication is lost. | B |
| VDD | 1 | SDQ | Loss of functionality. Communication is lost. | B |
Table 4-5 Pin FMA for Device Pins Short-Circuited to Supply
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| ADDR | 3 | There can be an absolute maximum exceedance if the ADDR pin is used for address decoding. | A |
| In other cases, no device damage. | D | ||
| GND | 4 | Device not powered. Device not functional. Verify that the absolute maximum ratings for all device pins are met, otherwise device damage is plausible. | B |
| IO0 | 6 | If I/O is used for controlling an external component, functionality is lost. | B |
| If I/O is not being used, then no effect. | D | ||
| IO1 | 7 | If I/O is used for controlling an external component, functionality is lost. | B |
| If I/O is not being used, then no effect. | D | ||
| IO2 | 8 | If I/O is used for controlling an external component, functionality is lost. | B |
| If I/O is not being used, then no effect. | D | ||
| IO3 | 5 | If I/O is used for controlling an external component, functionality is lost. | B |
| If I/O is not being used, then no effect. | D | ||
| SDQ | 3 | Loss of functionality. Communication is lost. | B |
| VDD | 1 | No effect. Normal operation. | D |