SFFS193A July   2022  – November 2022 DP83TC812R-Q1 , DP83TC812S-Q1

 

  1.   Trademarks
  2. 1Overview
  3. 2Functional Safety Failure In Time (FIT) Rates
  4. 3Failure Mode Distribution (FMD)
  5. 4Pin Failure Mode Analysis (Pin FMA) DP83TC812S-Q1
  6. 5Pin Failure Mode Analysis (Pin FMA) DP83TC812R-Q1
  7. 6Revision History

Failure Mode Distribution (FMD)

The failure mode distribution estimation for the DP83TC812S-Q1 and DP83TC812R-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity, and from best engineering judgment.

The failure modes listed in this section reflect random failure events and do not include failures resulting from misuse or overstress.

Table 3-1 Die Failure Modes and Distribution
Die Failure Modes Failure Mode Distribution (%)
Fault in MDI transmitter causing IEEE spec compliance issues 8
Fault in MDI transmitter causing high RF emissions 4
Fault in MDI receiver causing poor-link quality/link-loss 8
Fault in internal power circuits causing poor link quality and higher power consumption 12
Fault in internal clock circuits causing IEEE compliance issues and poor link-quality 8
Fault in GPIO causing higher RF emissions 8
Fault in GPIO causing Rgmii/JEDEC/Datasheet spec violation 8
Fault in ESD on MDI making IEC ESD performance lower than 8KV 4
Fault in ESD on GPIOs making CDM performance lower than 2KV. 4
Digital core has stuck or transient faults causing link-up or PCS faults 36