SFFS160 June   2021 UCC12041-Q1 , UCC12051-Q1

 

  1.   Trademarks
  2. 1Overview
  3. 2Functional Safety Failure In Time (FIT) Rates
  4. 3Failure Mode Distribution (FMD)
  5. 4Pin Failure Mode Analysis (Pin FMA)

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the UCC12051-Q1 and UCC12041-Q1 . The failure modes covered in this document include the typical pin-by-pin failure scenarios:

  • Pin short-circuited to Ground (see Table 4-2)
  • Pin open-circuited (see Table 4-3)
  • Pin short-circuited to an adjacent pin (see Table 4-4)
  • Pin short-circuited to supply (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality
BNo device damage, but loss of functionality
CNo device damage, but performance degradation
DNo device damage, no impact to functionality or performance

Figure 4-1 shows the UCC12051-Q1 and UCC12041-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the UCC12051-Q1 and UCC12041-Q1 data sheet.

Figure 4-1 Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

  • External pull-down resistor on SYNC to GNDP
  • External pull-up resistor on SYNC_OK to VINP
  • EN connected to VINP
  • NC pins 6-8 are connected to GNDP
  • SEL connected to VISO (5 VISO)
  • NC pins 10-12 are connected to GNDS
  • GNDP is considered as the Ground for pin 1 through 8
  • GNDS is considered as the Ground for pin 9 through 16
  • VINP is considered as the supply for pin 1 through 8
  • VISO is considered as the supply for pin 9 through 16
Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
Pin NamePin No.Description of Potential Failure Effect(s)(1)(2)Failure Effect Class
EN1Disabled state, VISO remains off (~ 0 V)B
GNDP2Normal functionality, VISO regulates to the programmed value set by SEL pinD
VINP3Will short externally provided VINP supply. Non-functional, no supply, VISO remains off (~ 0 V)B
SYNC4Normal functionality, VISO regulates to the programmed value set by SEL pinD
SYNC_OK5Normal functionality, VISO regulates to the programmed value set by SEL pinD
NC6Normal functionality, VISO regulates to the programmed value set by SEL pinD
NC7Normal functionality, VISO regulates to the programmed value set by SEL pinD
NC8Normal functionality, VISO regulates to the programmed value set by SEL pinD
GNDS9 Normal functionality, VISO regulates to the programmed value set by SEL pinD
NC10 Normal functionality, VISO regulates to the programmed value set by SEL pinD
NC11 Normal functionality, VISO regulates to the programmed value set by SEL pinD
NC12 Normal functionality, VISO regulates to the programmed value set by SEL pinD
SEL13Short SEL and VISO output to ground (~ 0 V, non-functional)B
VISO14Short VISO and SEL output to ground (~ 0 V, non-functional)B
GNDS15Normal functionality, VISO regulates to the programmed value set by SEL pinD
GNDS16Normal functionality, VISO regulates to the programmed value set by SEL pinD
(1) GNDP is considered as the Ground for pin 1 through 8
(2) GNDS is considered as the Ground for pin 9 through 16
Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
EN1Disabled state, VISO remains off (~ 0 V). 100-kΩ internal pull-downB
GNDP2No VISO outputB
VINP3Non-functional, no supply path, VISO remains off (~ 0 V)B
SYNC4Possible noise coupling leading to corruption of the internal oscillator. May result in an incorrectly regulated VISO DC value, unstable output, or inability to maintain VISO load line performanceC
SYNC_OK5Normal functionality, VISO regulates to the programmed value set by SEL pinD
NC6No impactD
NC7No impactD
NC8No impactD
GNDS9Normal functionality, VISO regulates to the programmed value set by SEL pin. Less than ideal grounding (through leadframe and pins 10, 11, 12, and15)D
NC10No impactD
NC11No impactD
NC12No impactD
SEL13Unsupported VISO selection state - VISO will most likely regulate to 3.7 V due to internal high impedance pull-down, but results may vary due to floating stateC
VISO14VISO output may go unstable due to absence of output cap (may not regulate as expected)C
GNDS15Normal functionality, VISO regulates to the programmed value set by SEL pin. Less than ideal grounding (through leadframe and pin 9), may see increased ripple on VISO output due to additional ground noiseD
GNDS16Normal functionality, VISO regulates to the programmed value set by SEL pinD
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin NamePin No.Shorted toDescription of Potential Failure Effect(s)Failure Effect Class
EN1GNDPDisabled state, VISO remains off (~ 0 V)B
GNDP2VINPWill short externally provided VINP supply; Non-functional, no supply, VISO remains off (~ 0 V)B
VINP3SYNCNormal functionality, VISO regulates to the programmed value set by SEL pinD
SYNC4SYNC_OKNormal functionality, VISO regulates to the programmed value set by SEL pinD
SYNC_OK5NCNormal functionality, VISO regulates to the programmed value set by SEL pinD
NC6NCNo impactD
NC7NCNo impactD
NC8N/AN/AD
GNDS9NCNo impactD
NC10NCNo impactD
NC11NCNo impactD
NC12SEL

SEL is connected to VISO. SEL shorted to NC means VISO shorted to GNDS, VISO is ~ 0 V, non-functional.

B
SEL13VISO Normal functionality, VISO regulates to 5 VD
VISO14GNDSWill short VISO output to ground (VISO is ~ 0 V, non-functional),B
GNDS15GNDSNormal functionality, VISO regulates to the programmed value set by SEL pinD
GNDS16N/AN/AD
Table 4-5 Pin FMA for Device Pins Short-Circuited to supply
Pin NamePin No.Description of Potential Failure Effect(s)(1)(2)Failure Effect Class
EN1Normal functional, VISO regulates to the programmed value set by SEL pinD
GNDP2 Will short to externally provided VINP supply. Non-functional, no supply, VISO remains off (~ 0 V)B
VINP3Normal functionality, VISO regulates to the programmed value set by SEL pinD
SYNC4Normal functionality, VISO regulates to the programmed value set by SEL pinD
SYNC_OK5Potential overstress/damage of open-drain device if external clock on SYNC is ignored/not used (pin is actively pulled low internally). VISO will still regulate to the programmed value set by SEL pin.A
NC6Will short to externally provided VINP supply. Non-functional, no supply, VISO remains off (~ 0 V)B
NC7Will short to externally provided VINP supply. Non-functional, no supply, VISO remains off (~ 0 V)B
NC8Will short to externally provided VINP supply. Non-functional, no supply, VISO remains off (~ 0 V)B
GNDS9 Will short VISO to ground (~ 0 V, non-functional)B
NC10 Will short VISO to ground (~ 0 V, non-functional)B
NC11 Will short VISO to ground (~ 0 V, non-functional)B
NC12 Will short VISO to ground (~ 0 V, non-functional)B
SEL13 Normal functionality, VISO regulates to 5VD
VISO14Normal functionality, VISO regulates to the programmed value set by SEL pinD
GNDS15Will short VISO to ground (~ 0 V, non-functional)B
GNDS16Will short VISO to ground (~ 0 V, non-functional)B
(1) VINP is considered as the supply for pin 1 through 8
(2) VISO is considered as the supply for pin 9 through 16