This section provides a Failure Mode Analysis
(FMA) of the pins for each of the device variants of DRV8244-Q1 as listed
below.
- HW variant in HVSSOP package
- SPI "S" variant in HVSSOP package
- SPI "P" variant in HVSSOP package
- HW variant in VQFN-HR
package
- SPI "S" variant in VQFN-HR
package
The failure modes covered in this document include the typical pin-by-pin failure
scenarios:
- Pin short-circuited to Ground
- Pin open-circuited
- Pin short-circuited to an adjacent pin
- Pin short-circuited to supply
The analysis also indicates how these pin
conditions can affect the device as per the failure effects classification in Table 4-1.
Table 4-1 TI Classification of Failure Effects| Class | Failure Effects |
|---|
| A | Potential device damage that
affects functionality |
| B | No device damage, but loss of
functionality |
| C | No device damage, but performance
degradation |
| D | No device damage, no impact to
functionality or performance |
Following are the
assumptions of use and the device configuration assumed for the pin FMA in this
section:
Figure 4-1 DRV824x-Q1 in Full Bridge
mode
- Test conditions:
- VVM = 13.5
V, TAmbient = 25°C , SPI "P" variant: VVDD = 5
V
- SPI "S" and "P" variant:
- DRVOFF, EN/IN1 pins
controlled by controller, PH/IN2 pin tied low
- IPROPI pin monitored
by controller, nFAULT pin monitoring optional
- Configurations: PH/EN
mode, SPI_IN unlocked with
- DRVOFF_SEL =
1'b0 (Pin and register control for redundant shutoff)
- EN_IN1_SEL =
1'b1 (Pin only control for PWM)
- PH_IN2_SEL =
1'b0 (Register only control for direction)
- HW variant:
-
- nSLEEP, DRVOFF,
EN/IN1, PH/IN2 pins controlled by controller
- nFAULT and IPROPI
pins monitored by controller
- Configuration: PWM
mode