SDAA301 March   2026 TPS25762-Q1 , TPS25763-Q1 , TPS25772-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2PD Controller Host Interface Description
    1. 2.1 TPS257xx-Q1 I2C Target Addresses
    2. 2.2 Host Interface Protocol
  6. 3TPS257xx-Q1 Telemetry Registers
    1. 3.1 STATUS Register (Address = 1Ah)
    2. 3.2 POWER PATH STATUS Register (Address = 26h)
    3. 3.3 THERMAL ENG PWR STATUS Register (Address = 96h)
    4. 3.4 DEVICE INFO Register (Address = 2Fh)
    5. 3.5 CUSTOM ID (Version Control) Register (Address = 06h)
  7. 4Summary
  8. 5References

3.2 POWER PATH STATUS Register (Address = 26h)

This RO register returns power path status and fault status parameters. When the host reads from the Port A target address (0x22 or 0x23), the register returns the status associated with Port A. When the host reads from the Port B target address (0x26 or 0x27), the register returns the status associated with Port B.

Table 3-2 POWER PATH STATUS Register Bit Field Descriptions
Bits Name Description
Byte 5: Power Path Common Status
7:4 Reserved Reserved
3 VIN Good FE VIN Good falling edge. Asserted if a UVLO condition is detected on VIN (Falling edge below VIN Good threshold).
2 VIN Ovp VIN OVP. Asserted if an OVP condition exists on VIN.
1:0 Reserved Reserved
Byte 4: VBUS, VCONN, DPDM Fault Status
7:6 Reserved Reserved
5 DPDM Ovp DPDM OVP. Asserted if an OVP condition exists on DP DM.
4 Vconn Ovp VCONN OVP. Asserted if an OVP condition exists on VCONN.
3 Vconn Ocp VCONN OCP. Asserted if an OCP condition exists on VCONN.
2 Vconn Tsd VCONN TSD. Asserted if a TSD condition exists on VCONN.
1 VBUS Uvp VBUS UVP. Asserted if a UVP condition exists on VBUS.
0 VBUS Ovp VBUS OVP. Asserted if an OVP condition exists on VBUS.
Bytes 1-3: Reserved
23:0 Reserved Reserved