SDAA131A January   2026  – July 2026 UCD91160 , UCD91320

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Design Considerations
    1. 2.1 Resistor Values and Regulation Range
    2. 2.2 DPWM Frequency and Vout Resolution
    3. 2.3 Margin DPWM Output Filtering
      1. 2.3.1 Attenuation by RC Filter
      2. 2.3.2 Attenuation by Loop Response
    4. 2.4 Impact on Power Supply Normal Operation
    5. 2.5 Impact on Power Supply Soft Start
    6. 2.6 Initial Duty Cycle
  6. 3Design Procedure
  7. 4Summary
  8. 5References
  9. 6Revision History
Application Note

Design Voltage Margining Circuit for UCD91xxx Power Sequencer and System Manager