TCA9539 Low Voltage 16-Bit I2C and SMBus Low-Power I/O Expander with Interrupt Output, Reset Pin, and Configuration Registers
- SCPS202C October 2009 – May 2016 TCA9539
  
  PRODUCTION DATA.

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DATA SHEET

TCA9539 Low Voltage 16-Bit I2C and SMBus Low-Power I/O Expander with Interrupt Output, Reset Pin, and Configuration Registers

1 Features

I²C to Parallel Port Expander
Low Standby-Current Consumption
Open-Drain Active-Low Interrupt Output
Active-Low Reset Input
5-V Tolerant I/O Ports
Compatible With Most Microcontrollers
400-kHz Fast I²C Bus
Input and Output Configuration Register
Polarity Inversion Register
Internal Power-on Reset
No Glitch on Power Up
Noise Filter on SCL and SDA Inputs
Address by Two Hardware Address Pins for Use of up to Four Devices
Latched Outputs With High-Current Drive Capability for Directly Driving LEDs
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 1000-V Charged-Device Model (C101)

2 Applications

Servers
Routers (Telecom Switching Equipment)
Personal Computers, smartphones
Industrial Automation
I²C GPIO Expansion

3 Description

The TCA9539 is a 24-pin device that provides 16 bits of general purpose parallel input and output (I/O) expansion for the two-line bidirectional I²C bus (or SMBus protocol). The device can operate with a power supply voltage (V_CC) range from 1.65 V to 5.5 V. The device supports 100-kHz (I²C Standard mode) and 400-kHz (I²C Fast mode) clock frequencies. I/O expanders such as the TCA9539 provide a simple solution when additional I/Os are needed for switches, sensors, push-buttons, LEDs, fans, and other similar devices.

The features of the TCA9539 include an interrupt that is generated on the INT pin whenever an input port changes state. The A0 and A1 hardware selectable address pins allow up to four TCA9539 devices on the same I²C bus. The device can be reset to its default state by cycling the power supply and causing a power-on-reset. Also, the TCA9539 has a hardware RESET pin that can be used to reset the device to its default state.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TCA9539	TSSOP (24)	7.80 mm × 4.40 mm
	WQFN (24)	4.00 mm × 4.00 mm
	VQFN (24)	4.00 mm × 4.00 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

TCA9539 Application_schematic_SCPS202C.gif

4 Revision History

Changes from B Revision (October 2015) to C Revision

Made changes to Interrupt (INT) Output and Reads sectionGo
Made changes to Recommended Operating ConditionsGo
Made changes to Electrical CharacteristicsGo
Added I_OL for different T_j Go
Removed ΔI_CC spec from the Electrical Characteristics table, added ΔI_CC typical characteristics graph Go
Changed I_CC standby into different input states, with increased maximums Go
Changed C_io maximum Go
Clarified interrupt reset time (t_ir) with respect to falling edge of ACK related SCL pulse. Go
Updated Figure 33 and Figure 34Go
Power on reset requirements relaxed Go

Changes from A Revision (September 2009) to B Revision

Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. Go
Added RGE package.Go
Added Thermal Information table Go
Added "Time to reset; V_CC = 1.65 V - 2.3 V" parameter to RESET Timing Requirements table. Go
Added "Output data valid; V_CC = 1.65 V - 2.3 V to Switching Characteristics table. Go

5 Pin Configuration and Functions

PW Package

24-Pins TSSOP

Top View

RTW, RGE Package

24-Pins WQFN, VQFN

Top View

Pin Functions

NAME	NO.		I/O	DESCRIPTION
NAME	TSSOP (PW)	QFN (RTW, RGE)	I/O	DESCRIPTION
A0	21	18	I	Address input. Connect directly to V_CC or ground
A1	2	23	I	Address input. Connect directly to V_CC or ground
GND	12	9	—	Ground
INT	1	22	O	Interrupt open-drain output. Connect to V_CC through a pull-up resistor
RESET	3	24	I	Active-low reset input. Connect to V_CC through a pull-up resistor if no active connection is used
P00	4	1	I/O	P-port input-output. Push-pull design structure. At power on, P00 is configured as an input
P01	5	2	I/O	P-port input-output. Push-pull design structure. At power on, P01 is configured as an input
P02	6	3	I/O	P-port input-output. Push-pull design structure. At power on, P02 is configured as an input
P03	7	4	I/O	P-port input-output. Push-pull design structure. At power on, P03 is configured as an input
P04	8	5	I/O	P-port input-output. Push-pull design structure. At power on, P04 is configured as an input
P05	9	6	I/O	P-port input-output. Push-pull design structure. At power on, P05 is configured as an input
P06	10	7	I/O	P-port input-output. Push-pull design structure. At power on, P06 is configured as an input
P07	11	8	I/O	P-port input-output. Push-pull design structure. At power on, P07 is configured as an input
P10	13	10	I/O	P-port input-output. Push-pull design structure. At power on, P10 is configured as an input
P11	14	11	I/O	P-port input-output. Push-pull design structure. At power on, P11 is configured as an input
P12	15	12	I/O	P-port input-output. Push-pull design structure. At power on, P12 is configured as an input
P13	16	13	I/O	P-port input-output. Push-pull design structure. At power on, P13 is configured as an input
P14	17	14	I/O	P-port input-output. Push-pull design structure. At power on, P14 is configured as an input
P15	18	15	I/O	P-port input-output. Push-pull design structure. At power on, P15 is configured as an input
P16	19	16	I/O	P-port input-output. Push-pull design structure. At power on, P16 is configured as an input
P17	20	17	I/O	P-port input-output. Push-pull design structure. At power on, P17 is configured as an input
SCL	22	19	I	Serial clock bus. Connect to V_CC through a pull-up resistor
SDA	23	20	I/O	Serial data bus. Connect to V_CC through a pull-up resistor
V_CC	24	21	—	Supply voltage

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

			MIN	MAX	UNIT
V_CC	Supply voltage		–0.5	6	V
V_I	Input voltage⁽²⁾		–0.5	6	V
V_O	Output voltage ⁽²⁾		–0.5	6	V
I_IK	Input clamp current	V_I < 0		–20	mA
I_OK	Output clamp current	V_O < 0		–20	mA
I_IOK	Input-output clamp current	V_O < 0 or V_O > V_CC		±20	mA
I_OL	Continuous output low current	V_O = 0 to V_CC		50	mA
I_OH	Continuous output high current	V_O = 0 to V_CC		–50	mA
I_CC	Continuous current through GND			–250	mA
I_CC	Continuous current through V_CC			160	mA
T_j(MAX)	Maximum junction temperature			100	°C
T_stg	Storage temperature		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101 ⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

6.3 Recommended Operating Conditions

				MIN	MAX	UNIT
V_CC	Supply voltage			1.65	5.5	V
V_IH	High-level input voltage	SCL, SDA		0.7 × V_CC	V_CC ^⁽¹⁾	V
V_IH	High-level input voltage	A0, A1, RESET, P07–P00, P10–P17		0.7 × V_CC	5.5	V
V_IL	Low-level input voltage	SCL, SDA, A0, A1, RESET, P07–P00, P10–P17		–0.5	0.3 × V_CC	V
I_OH	High-level output current	P07–P00, P17–P10			–10	mA
I_OL	Low-level output current⁽²⁾	P00–P07, P10–P17	T_j ≤ 65°C		25	mA
			T_j ≤ 85°C		18
			T_j ≤ 100°C		11
I_OL	Low-level output current⁽²⁾	INT, SDA	T_j ≤ 85°C		6	mA
I_OL	Low-level output current⁽²⁾	INT, SDA	T_j ≤ 100°C		3.5	mA
T_A	Operating free-air temperature			–40	85	°C

(1) For voltages applied above V_CC, an increase in I_CC will result.

(2) The values shown apply to specific junction temperatures, which depend on the R_θJA of the package used. See the Calculating Junction Temperature and Power Dissipation section on how to calculate the junction temperature.

6.4 Thermal Information

THERMAL METRIC ⁽¹⁾		TCA9539			UNIT
		PW (TSSOP)	RTW (WQFN)	RGE (VQFN)
		24 PINS	24 PINS	24 PINS
R_θJA	Junction-to-ambient thermal resistance	108.8	43.6	48.4	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	54.	46.2	58.1	°C/W
R_θJB	Junction-to-board thermal resistance	62.8	22.1	27.1	°C/W
ψ_JT	Junction-to-top characterization parameter	11.1	1.5	3.3	°C/W
ψ_JB	Junction-to-board characterization parameter	62.3	22.2	27.2	°C/W
R_θJC(bottom)	Junction-to-case (bottom) thermal resistance	—	10.7	15.3	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS		V_CC	MIN	TYP ⁽¹⁾	MAX	UNIT
V_IK	Input diode clamp voltage	I_I = –18 mA		1.65 V to 5.5 V	–1.2			V
V_PORR	Power-on reset voltage, V_CC rising	V_I = V_CC or GND, I_O = 0		1.65 V to 5.5 V		1.2	1.5	V
V_PORF	Power-on reset voltage, V_CC falling	V_I = V_CC or GND, I_O = 0		1.65 V to 5.5 V	0.75	1		V
V_OH	P-port high-level output voltage ⁽²⁾	I_OH = –8 mA		1.65 V	1.2			V
				2.3 V	1.8
				3 V	2.6
				4.75 V	4.1
		I_OH = –10 mA		1.65 V	1
				2.3 V	1.7
				3 V	2.5
				4.75 V	4
I_OL	SDA	V_OL = 0.4 V		1.65 V to 5.5 V	3			mA
	P port ⁽³⁾	V_OL = 0.5 V		1.65 V to 5.5 V	8
	P port ⁽³⁾	V_OL = 0.7 V		1.65 V to 5.5 V	10
	INT	V_OL = 0.4 V			3
I_I	SCL, SDA	V_I = V_CC or GND		1.65 V to 5.5 V			±1	μA
I_I	A0, A1, RESET	V_I = V_CC or GND		1.65 V to 5.5 V			±1	μA
I_IH	P port	V_I = V_CC		1.65 V to 5.5 V			1	μA
I_IL	P port	V_I = GND		1.65 V to 5.5 V			–1	μA
I_CC	Operating mode	V_I = V_CC or GND, I_O = 0, I/O = inputs, f_SCL = 400 kHz, no load		5.5 V		22	40	μA
				3.6 V		11	30
				2.7 V		8	19
				1.95 V		5	11
	Standby mode	V_I = V_CC or GND, I_O = 0, I/O = inputs, f_SCL = 0 kHz, no load	V_I = V_CC	5.5 V		1.5	3.9
				3.6 V		0.9	2.2
				2.7 V		0.6	1.8
				1.95 V		0.4	1.5
			V_I = GND	5.5 V		1.5	8.7
				3.6 V		0.9	4
				2.7 V		0.6	3
				1.95 V		0.4	2.2
C_i	SCL	V_I = V_CC or GND		1.65 V to 5.5 V		3	8	pF
C_io	SDA	V_IO = V_CC or GND		1.65 V to 5.5 V		3	9.5	pF
C_io	P port	V_IO = V_CC or GND		1.65 V to 5.5 V		3.7	9.5	pF

(1) All typical values are at nominal supply voltage (1.8-, 2.5-, 3.3-, or 5-V V_CC) and T_A = 25°C.

(2) Each I/O must be externally limited to a maximum of 25 mA, and each octal (P07–P00 and P17–P10) must be limited to a maximum current of 100 mA, for a device total of 200 mA.

(3) The total current sourced by all I/Os must be limited to 160 mA (80 mA for P07–P00 and 80 mA for P17–P10).

6.6 I²C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 19)

			MIN	MAX	UNIT
I²C BUS—STANDARD MODE
f_scl	I²C clock frequency		0	100	kHz
t_sch	I²C clock high time		4		µs
t_scl	I²C clock low time		4.7		µs
t_sp	I²C spike time			50	ns
t_sds	I²C serial-data setup time		250		ns
t_sdh	I²C serial-data hold time		0		ns
t_icr	I²C input rise time			1000	ns
t_icf	I²C input fall time			300	ns
t_ocf	I²C output fall time	10-pF to 400-pF bus		300	ns
t_buf	I²C bus free time between stop and start		4.7		µs
t_sts	I²C start or repeated start condition setup		4.7		µs
t_sth	I²C start or repeated start condition hold		4		µs
t_sps	I²C stop condition setup		4		µs
t_vd(data)	Valid data time	SCL low to SDA output valid		3.45	µs
t_vd(ack)	Valid data time of ACK condition	ACK signal from SCL low to SDA (out) low		3.45	µs
C_b	I²C bus capacitive load			400	pF

			MIN	MAX	UNIT
I²C BUS—FAST MODE
f_scl	I²C clock frequency		0	400	kHz
t_sch	I²C clock high time		0.6		µs
t_scl	I²C clock low time		1.3		µs
t_sp	I²C spike time			50	ns
t_sds	I²C serial-data setup time		100		ns
t_sdh	I²C serial-data hold time		0		ns
t_icr	I²C input rise time		20	300	ns
t_icf	I²C input fall time		20 × (V_CC / 5.5 V)	300	ns
t_ocf	I²C output fall time	10-pF to 400-pF bus	20 × (V_CC / 5.5 V)	300	ns
t_buf	I²C bus free time between stop and start		1.3		µs
t_sts	I²C start or repeated start condition setup		0.6		µs
t_sth	I²C start or repeated start condition hold		0.6		µs
t_sps	I²C stop condition setup		0.6		µs
t_vd(data)	Valid data time	SCL low to SDA output valid		0.9	µs
t_vd(ack)	Valid data time of ACK condition	ACK signal from SCL low to SDA (out) low		0.9	µs
C_b	I²C bus capacitive load			400	pF

6.7 RESET Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 22)

		MIN	UNIT
t_W	Reset pulse duration	6	ns
t_REC	Reset recovery time	0	ns
t_RESET	Time to reset; for V_CC = 2.3 V - 5.5 V	400	ns
t_RESET	Time to reset; for V_CC = 1.65 V - 2.3 V	550	ns

6.8 Switching Characteristics

over recommended operating free-air temperature range, C_L ≤ 100 pF (unless otherwise noted) (see Figure 20 and Figure 21)

PARAMETER		FROM (INPUT)	TO (OUTPUT)	MIN	MAX	UNIT
t_iv	Interrupt valid time	P port	INT		4	μs
t_ir	Interrupt reset delay time	SCL	INT		4	μs
t_pv	Output data valid; For V_CC = 2.3 V - 5.5 V	SCL	P port		200	ns
t_pv	Output data valid; For V_CC = 1.65 V - 2.3 V	SCL	P port		300	ns
t_ps	Input data setup time	P port	SCL	150		ns
t_ph	Input data hold time	P port	SCL	1		μs

6.9 Typical Characteristics

T_A = 25°C (unless otherwise noted)

Figure 1. Supply Current vs Temperature for Different Supply Voltage (V_CC)

Figure 3. Supply Current vs Supply Voltage for Different Temperature (T_A)

Figure 5. I/O Sink Current vs Output Low Voltage for Different Temperature (T_A) for V_CC = 1.8 V

Figure 7. I/O Sink Current vs Output Low Voltage for Different Temperature (T_A) for V_CC = 3.3 V

Figure 9. I/O Sink Current vs Output Low Voltage for Different Temperature (T_A) for V_CC = 5.5 V

Figure 11. I/O Source Current vs Output High Voltage for Different Temperature (T_A) for V_CC = 1.65 V

Figure 13. I/O Source Current vs Output High Voltage for Different Temperature (T_A) for V_CC = 2.5 V

Figure 15. I/O Source Current vs Output High Voltage for Different Temperature (T_A) for V_CC = 5 V

Figure 17. V_CC – V_OH Voltage vs Temperature for Different V_CC

Figure 2. Standby Supply Current vs Temperature for Different Supply Voltage (V_CC)

Figure 4. I/O Sink Current vs Output Low Voltage for Different Temperature (T_A) for V_CC = 1.65 V

Figure 6. I/O Sink Current vs Output Low Voltage for Different Temperature (T_A) for V_CC = 2.5 V

Figure 8. I/O Sink Current vs Output Low Voltage for Different Temperature (T_A) for V_CC = 5 V

Figure 10. II/O Low Voltage vs Temperature for Different V_CC and I_OL

Figure 12. I/O Source Current vs Output High Voltage for Different Temperature (T_A) for V_CC = 1.8 V

Figure 14. I/O Source Current vs Output High Voltage for Different Temperature (T_A) for V_CC = 3.3 V

Figure 16. I/O Source Current vs Output High Voltage for Different Temperature (T_A) for V_CC = 5.5 V

Figure 18. Δ I_CC vs Temperature for Different V_CC (V_I = V_CC – 0.6 V)

7 Parameter Measurement Information

A. C_L includes probe and jig capacitance.

B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O = 50 Ω, t_r/t_f ≤ 30 ns.

C. All parameters and waveforms are not applicable to all devices.

Figure 19. I²C Interface Load Circuit and Voltage Waveforms

A. C_L includes probe and jig capacitance.

B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O = 50 Ω, t_r/t_f ≤ 30 ns.

C. All parameters and waveforms are not applicable to all devices.

Figure 20. Interrupt Load Circuit and Voltage Waveforms

A. C_L includes probe and jig capacitance.

B. t_pv is measured from 0.7 × V_CC on SCL to 50% I/O (Pn) output.

C. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O = 50 Ω, t_r/t_f ≤ 30 ns.

D. The outputs are measured one at a time, with one transition per measurement.

E. All parameters and waveforms are not applicable to all devices.

Figure 21. P-Port Load Circuit and Voltage Waveforms

A. C_L includes probe and jig capacitance.

B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O = 50 Ω, t_r/t_f ≤ 30 ns.

C. The outputs are measured one at a time, with one transition per measurement.

D. I/Os are configured as inputs.

E. All parameters and waveforms are not applicable to all devices.

Figure 22. Reset Load Circuits and Voltage Waveforms

8 Detailed Description

8.1 Overview

The TCA9539 is a 16-bit Input-Output expander for the two-line bidirectional bus (I²C) designed for 1.65-V to 5.5-V V_CC operation. It provides general-purpose remote I/O expansion for most microcontroller families via the I²C interface ,serial clock (SCL) and serial data (SDA).

The TCA9539 consists of two 8-bit Configuration (input or output selection), Input Port, Output Port, and Polarity Inversion (active-high or active-low operation) registers. At power-on, the I/Os are configured as inputs. The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration register bits. The data for each input or output is kept in the corresponding Input or output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master.

The system master can reset the TCA9539 in the event of a time-out or other improper operation by asserting a low in the RESET input. The power-on reset puts the registers in their default state and initializes the I²C-SMBus state machine. Asserting RESET causes the same reset-initialization to occur without depowering the part.

The TCA9539 open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed.

INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I²C bus. Thus, the TCA9539 can remain a simple slave device.

The device outputs (latched) have high-current drive capability for directly driving LEDs. The device has low current consumption.

The TCA9539 is similar to the PCA9555, except for the removal of the internal I/O pull-up resistor, which greatly reduces power consumption when the I/Os are held low, replacement of A2 with RESET, and a different address range. The TCA9539 is equivalent to the PCA9539 with lower voltage support (down to V_CC = 1.65 V), and also improved power-on-reset circuitry for different application scenarios.

Two hardware pins (A0 and A1) are used to program and vary the fixed I²C address and allow up to four devices to share the same I²C bus or SMBus.

8.2 Functional Block Diagram

A. Pin numbers shown are for PW package.

B. All I/Os are set to inputs at reset.

Figure 23. Logic Diagram (Positive Logic)

1. At power-on reset, all registers return to default values.

Figure 24. Simplified Schematic of P-Port I/Os

8.3 Feature Description

8.3.1 I/O Port

When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The input voltage may be raised above V_CC to a maximum of 5.5 V.

If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output Port register. In this case, there are low-impedance paths between the I/O pin and either V_CC or GND. The external voltage applied to this I/O pin must not exceed the recommended levels for proper operation.

8.3.2 RESET Input

A reset can be accomplished by holding the RESET pin low for a minimum of t_W. The TCA9539 registers and I²C/SMBus state machine are held in their default states until RESET is once again high. This input requires a pull-up resistor to V_CC, if no active connection is used.

8.3.3 Interrupt (INT) Output

An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time t_iv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge (ACK) bit after the rising edge of the SCL signal. Note that the INT is reset at the ACK just before the byte of changed data is sent. Interrupts that occur during the ACK clock pulse can be lost (or be very short) because of the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.

Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register. Because each 8-bit port is read independently, the interrupt caused by port 0 is not cleared by a read of port 1, or vice versa.

INT has an open-drain structure and requires a pull-up resistor to V_CC.

8.4 Device Functional Modes

8.4.1 Power-On Reset

When power (from 0 V) is applied to V_CC, an internal power-on reset holds the TCA9539 in a reset condition until V_CC has reached V_POR _R. At that point, the reset condition is released and the TCA9539 registers and I²C-SMBus state machine initialize to their default states. After that, V_CC must be lowered to below V_PORF and then back up to the operating voltage for a power-reset cycle.

8.5 Programming

8.5.1 I²C Interface

The TCA9539 has a standard bidirectional I²C interface that is controlled by a master device in order to be configured or read the status of this device. Each slave on the I²C bus has a specific device address to differentiate between other slave devices that are on the same I²C bus. Many slave devices require configuration upon startup to set the behavior of the device. This is typically done when the master accesses internal register maps of the slave, which have unique register addresses. A device can have one or multiple registers where data is stored, written, or read. For more information see Understanding the I²C Bus, SLVA704.

The physical I²C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines must be connected to V_CC through a pull-up resistor. The size of the pull-up resistor is determined by the amount of capacitance on the I²C lines. For further details, see I²C Pull-up Resistor Calculation, SLVA689. Data transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are high after a STOP condition. See Table 1.

Figure 25 and Figure 26 show the general procedure for a master to access a slave device:

If a master wants to send data to a slave:
- Master-transmitter sends a START condition and addresses the slave-receiver.
- Master-transmitter sends data to slave-receiver.
- Master-transmitter terminates the transfer with a STOP condition.
If a master wants to receive or read data from a slave:
- Master-receiver sends a START condition and addresses the slave-transmitter.
- Master-receiver sends the requested register to read to slave-transmitter.
- Master-receiver receives data from the slave-transmitter.
- Master-receiver terminates the transfer with a STOP condition.

Figure 25. Definition of Start and Stop Conditions

Figure 26. Bit Transfer

Table 1 shows the interface definition.

Table 1. Interface Definition

BYTE	BIT
BYTE	7 (MSB)	6	5	4	3	2	1	0 (LSB)
I²C slave address	H	H	H	L	H	A1	A0	R/W
P0x I/O data bus	P07	P06	P05	P04	P03	P02	P01	P00
P1x I/O data bus	P17	P16	P15	P14	P13	P12	P11	P10

8.6 Register Maps

8.6.1 Device Address

Figure 27 shows the address byte of the TCA9539.

Figure 27. TCA9539 Address

Table 2 shows the address reference of the TCA9539.

Table 2. Address Reference

INPUTS		I²C BUS SLAVE ADDRESS
A1	A0	I²C BUS SLAVE ADDRESS
L	L	116 (decimal), 0x74 (hexadecimal)
L	H	117 (decimal), 0x75 (hexadecimal)
H	L	118 (decimal), 0x76 (hexadecimal)
H	H	119 (decimal), 0x77 (hexadecimal)

The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read operation, while a low (0) selects a write operation.

Note that the I²C addresses shown above are the 7-bit, right-justified hexadecimal values.

8.6.2 Control Register and Command Byte

Following the successful acknowledgment of the address byte, the bus master sends a command byte shown in Table 3 that is stored in the control register in the TCA9539. Three bits of this data byte state the operation (read or write) and the internal register (input, output, Polarity Inversion or Configuration) that is affected. This register can be written or read through the I²C bus. The command byte is sent only during a write transmission.

When a command byte has been sent, the register pair that was addressed continues to be accessed by reads until a new command byte has been sent. Figure 28 shows the control register bits.

Figure 28. Control Register Bits

Table 3. Command Byte

CONTROL REGISTER BITS			COMMAND BYTE (HEX)	REGISTER	PROTOCOL	POWER-UP DEFAULT
B2	B1	B0	COMMAND BYTE (HEX)	REGISTER	PROTOCOL	POWER-UP DEFAULT
0	0	0	0x00	Input Port 0	Read byte	xxxx xxxx
0	0	1	0x01	Input Port 1	Read byte	xxxx xxxx
0	1	0	0x02	Output Port 0	Read/write byte	1111 1111
0	1	1	0x03	Output Port 1	Read/write byte	1111 1111
1	0	0	0x04	Polarity Inversion Port 0	Read/write byte	0000 0000
1	0	1	0x05	Polarity Inversion Port 1	Read/write byte	0000 0000
1	1	0	0x06	Configuration Port 0	Read/write byte	1111 1111
1	1	1	0x07	Configuration Port 1	Read/write byte	1111 1111

8.6.3 Register Descriptions

The Input Port registers (registers 0 and 1) shown in Table 4 reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these registers have no effect. The default value, X, is determined by the externally applied logic level.

Before a read operation, a write transmission is sent with the command byte to indicate to the I²C device that the Input Port register is accessed next. See the Writes section for more information and examples.

Table 4. Registers 0 And 1 (Input Port Registers)

Bit	I0.7	I0.6	I0.5	I0.4	I0.3	I0.2	I0.1	I0.0
Default	X	X	X	X	X	X	X	X
Bit	I1.7	I1.6	I1.5	I1.4	I1.3	I1.2	I1.1	I1.0
Default	X	X	X	X	X	X	X	X

The Output Port registers (registers 2 and 3) shown in Table 5 show the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.

Table 5. Registers 2 And 3 (Output Port Registers)

Bit	O0.7	O0.6	O0.5	O0.4	O0.3	O0.2	O0.1	O0.0
Default	1	1	1	1	1	1	1	1
Bit	O1.7	O1.6	O1.5	O1.4	O1.3	O1.2	O1.1	O1.0
Default	1	1	1	1	1	1	1	1

The Polarity Inversion registers (registers 4 and 5) shown in Table 6 allow Polarity Inversion of pins defined as inputs by the Configuration register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin's original polarity is retained.

Table 6. Registers 4 And 5 (Polarity Inversion Registers)

Bit	N0.7	N0.6	N0.5	N0.4	N0.3	N0.2	N0.1	N0.0
Default	0	0	0	0	0	0	0	0
Bit	N1.7	N1.6	N1.5	N1.4	N1.3	N1.2	N1.1	N1.0
Default	0	0	0	0	0	0	0	0

The Configuration registers (registers 6 and 7) shown in Table 7 configure the directions of the I/O pins. If a bit in this register is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is cleared to 0, the corresponding port pin is enabled as an output.

Table 7. Registers 6 And 7 (Configuration Registers)

Bit	C0.7	C0.6	C0.5	C0.4	C0.3	C0.2	C0.1	C0.0
Default	1	1	1	1	1	1	1	1
Bit	C1.7	C1.6	C1.5	C1.4	C1.3	C1.2	C1.1	C1.0
Default	1	1	1	1	1	1	1	1

8.6.3.1 Bus Transactions

Data is exchanged between the master and the TCA9539 through write and read commands, and this is accomplished by reading from or writing to registers in the slave device.

Registers are locations in the memory of the slave which contain information, whether it be the configuration information or some sampled data to send back to the master. The master must write information to these registers in order to instruct the slave device to perform a task.

8.6.3.1.1 Writes

To write on the I²C bus, the master sends a START condition on the bus with the address of the slave, as well as the last bit (the R/W bit) set to 0, which signifies a write. After the slave sends the acknowledge bit, the master then sends the register address of the register to which it wishes to write. The slave acknowledges again, letting the master know it is ready. After this, the master starts sending the register data to the slave until the master has sent all the data necessary (which is sometimes only a single byte), and the master terminates the transmission with a STOP condition.

See the Register Descriptions section to see list of the TCA9539s internal registers and a description of each one.

Figure 29 shows an example of writing a single byte to a slave register.

Figure 29. Write to Register

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Figure 30. Write to the Polarity Inversion Register

Figure 31. Write to Output Port Registers

8.6.3.1.2 Reads

Reading from a slave is very similar to writing, but requires some additional steps. In order to read from a slave, the master must first instruct the slave which register it wishes to read from. This is done by the master starting off the transmission in a similar fashion as the write, by sending the address with the R/W bit equal to 0 (signifying a write), followed by the register address it wishes to read from. When the slave acknowledges this register address, the master sends a START condition again, followed by the slave address with the R/W bit set to 1 (signifying a read). This time, the slave acknowledges the read request, and the master releases the SDA bus but continues supplying the clock to the slave. During this part of the transaction, the master becomes the master-receiver, and the slave becomes the slave-transmitter.

The master continues to send out the clock pulses, but releases the SDA line so that the slave can transmit data. At the end of every byte of data, the master sends an ACK to the slave, letting the slave know that it is ready for more data. When the master has received the number of bytes it is expecting, it sends a NACK, signaling to the slave to halt communications and release the bus. The master follows this up with a STOP condition.

See the Register Descriptions section for the list of the TCA9539s internal registers and a description of each one.

Figure 32 shows an example of reading a single byte from a slave register.

Figure 32. Read from Register

After a restart, the value of the register defined by the command byte matches the register being accessed when the restart occurred. For example, if the command byte references Input Port 1 before the restart, the restart occurs when Input Port 0 is being read. The original command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked into the register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read, but the data now reflect the information in the other register in the pair. For example, if Input Port 1 is read, the next byte read is Input Port 0.

Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus master must not acknowledge the data.

A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (Read Input Port register).

B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data transfer from the P port (see Figure 32 for these details).

Figure 33. Read Input Port Register, Scenario 1

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Figure 34. Read Input Port Register, Scenario 2

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

Applications of the TCA9539 has this device connected as a slave to an I²C master (processor), and the I²C bus may contain any number of other slave devices. The TCA9539 is typically in a remote location from the master, placed close to the GPIOs to which the master must monitor or control.

IO Expanders such as the TCA9539 are typically used for controlling LEDs (for feedback or status lights), controlling enable or reset signals of other devices, and even reading the outputs of other devices or buttons.

9.2 Typical Application

Figure 35 shows an application in which the TCA9539 can be used.

A. Device address is configured as 1110100 for this example.

B. P00, P02, and P03 are configured as outputs.

C. P01 and P04 to P17 are configured as inputs.

D. Pin numbers shown are for the PW package.

Figure 35. Application Schematic

9.2.1 Design Requirements

9.2.1.1 Calculating Junction Temperature and Power Dissipation

When designing with this device, it is important that the Recommended Operating Conditions not be violated. Many of the parameters of this device are rated based on junction temperature. So junction temperature must be calculated in order to verify that safe operation of the device is met. The basic equation for junction temperature is shown in Equation 1.

Equation 1. TCA9539 Equation_01_SCPS254.gif

θ_JA is the standard junction to ambient thermal resistance measurement of the package, as seen in Thermal Information table. P_d is the total power dissipation of the device, and the approximation is shown in Equation 2.

Equation 2. TCA9539 Equation_02_SCPS254.gif

Equation 2 is the approximation of power dissipation in the device. The equation is the static power plus the summation of power dissipated by each port (with a different equation based on if the port is outputting high, or outputting low. If the port is set as an input, then power dissipation is the input leakage of the pin multiplied by the voltage on the pin). Note that this ignores power dissipation in the INT and SDA pins, assuming these transients to be small. They can easily be included in the power dissipation calculation by using Equation 3 to calculate the power dissipation in INT or SDA while they are pulling low, and this gives maximum power dissipation.

Equation 3. TCA9539 Equation_03_SCPS254.gif

Equation 3 shows the power dissipation for a single port which is set to output low. The power dissipated by the port is the V_OL of the port multiplied by the current it is sinking.

Equation 4. TCA9539 Equation_04_SCPS254.gif

Equation 4 shows the power dissipation for a single port which is set to output high. The power dissipated by the port is the current sourced by the port multiplied by the voltage drop across the device (difference between V_CC and the output voltage).

9.2.1.2 Minimizing I_CC When I/Os Control LEDs

When an I/O is used to control an LED, normally it is connected to V_CC through a resistor see Figure 35. Because the LED acts as a diode, when the LED is off, the I/O V_IN is about 1.2 V less than V_CC. The ΔI_CC parameter in the Electrical Characteristics table shows how I_CC increases as V_IN becomes lower than V_CC. For battery-powered applications, it is essential that the voltage of I/O pins is greater than or equal to V_CC, when the LED is off, to minimize current consumption.

Figure 36 shows a high-value resistor in parallel with the LED. Figure 37 shows V_CC less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O V_CC at or above V_CC and prevent additional supply-current consumption when the LED is off.

Figure 36. High-Value Resistor in Parallel with LED

Figure 37. Device Supplied by Lower Voltage

9.2.2 Detailed Design Procedure

The pull-up resistors, R_P, for the SCL and SDA lines need to be selected appropriately and take into consideration the total capacitance of all slaves on the I²C bus. The minimum pull-up resistance is a function of V_CC, V_OL,(max), and I_OL as shown in Equation 5.

Equation 5. TCA9539 desc_eq1_scps199.gif

The maximum pull-up resistance is a function of the maximum rise time, t_r (300 ns for fast-mode operation,
f_SCL = 400 kHz) and bus capacitance, C_b, see Equation 6.

Equation 6. TCA9539 desc_eq2_scps204.gif

The maximum bus capacitance for an I²C bus must not exceed 400 pF for standard-mode or fast-mode operation. The bus capacitance can be approximated by adding the capacitance of the TCA9554A, C_i for SCL or C_io for SDA, the capacitance of wires, connections and traces, and the capacitance of additional slaves on the bus.

9.2.3 Application Curves

Standard-mode	Fast-mode
(f_SCL= 100 kHz, t_r = 1 µs)	(f_SCL= 400 kHz, t_r= 300 ns)

Figure 38. Maximum Pull-Up Resistance (R_p(max)) vs Bus Capacitance (C_b)

V_OL = 0.2 × V_CC, I_OL = 2 mA when V_CC ≤ 2 V
V_OL = 0.4 V, I_OL = 3 mA when V_CC > 2 V

Figure 39. Minimum Pull-Up Resistance (R_p(min)) vs Pull-Up Reference Voltage (V_CC)

10 Power Supply Recommendations

10.1 Power-On Reset Requirements

In the event of a glitch or data corruption, the TCA9539 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.

The voltage waveform for a power-on reset is shown in Figure 40.

V_CC Is lowered below the POR threshold, then ramped back up to V_CC

Figure 40. Voltage Waveform for Power-On Reset

Table 8 specifies the performance of the power-on reset feature for the TCA9539.

Table 8. Recommended Supply Sequencing and Ramp Rates ⁽¹⁾

PARAMETER			MIN	TYP	MAX	UNIT
V_{CC_FT}	Fall rate	See Figure 40	0.1			ms
V_{CC_RT}	Rise rate	See Figure 40	0.1			ms
V_{CC_TRR}	Time to re-ramp (when V_CC drops to V_{POR_MIN} – 50 mV or when V_CC drops to GND)	See Figure 40	1			μs
V_{CC_GH}	The level (referenced to V_CC) that V_CC can glitch down to, but not cause a functional disruption when V_{CC_GW}	See Figure 41			1.2	V
V_{CC_MV}	The minimum voltage that V_CC can glitch down to without causing a reset (V_{CC_GH} must not be violated)	See Figure 41	1.5			V
V_{CC_GW}	Glitch width that will not cause a functional disruption	See Figure 41			10	μs
V_PORF	Voltage trip point of POR on falling V_CC		0.75	1		V
V_PORR	Voltage trip point of POR on rising V_CC			1.2	1.5	V

(1) T_A = –40°C to +85°C (unless otherwise noted)

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (V_{CC_GW}) and height (V_{CC_GH}) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 41 and Table 8 provide more information on how to measure these specifications.

Figure 41. Glitch Width and Glitch Height

V_POR is critical to the power-on reset. V_PORR is the voltage level at which the reset condition is released and all the registers and the I²C-SMBus state machine are initialized to their default states. The value of V_POR differs based on the V_CC being lowered to or from 0. Figure 42 and Table 8 provide more details on this specification.

Figure 42. V_POR

11 Layout

11.1 Layout Guidelines

For printed circuit board (PCB) layout of the TCA9539, common PCB layout practices must be followed but additional concerns related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I²C signal speeds.

In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power in the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. These capacitors must be placed as close to the TCA9539 as possible. These best practices are shown in Figure 43.

For the layout example provided in Figure 43, it would be possible to fabricate a PCB with only 2 layers by using the top layer for signal routing and the bottom layer as a split plane for power (V_CC) and ground (GND). However, a 4 layer board is preferable for boards with higher density signal routing. On a 4 layer PCB, it is common to route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate the other internal layer to a power plane. In a board layout using planes or split planes for power and ground, vias are placed directly next to the surface mount component pad which must attach to V_CC or GND and the via is connected electrically to the internal layer or the other side of the board. Vias are also used when a signal trace must be routed to the opposite side of the board, but this technique is not demonstrated in Figure 43.

11.2 Layout Example

Figure 43. TCA9539 Layout

12 Device and Documentation Support

Documentation Support

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12.2 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.