SCLK038 December   2023 SN54SC4T02-SEP

PRODUCTION DATA  

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Device Information
    1. 1.1 Device Details
  5. 2Total Dose Test Setup
    1. 2.1 Test Overview
    2. 2.2 Test Description and Facilities
    3. 2.3 Test Setup Details
      1. 2.3.1 Bias Diagram
    4. 2.4 Test Configuration and Condition
  6. 3TID Characterization Test Results
    1. 3.1 TID Characterization Summary Results
    2. 3.2 Specification Compliance Matrix
  7. 4Reference Documents
  8. 5Appendix: HDR TID Report Data

1 Device Information

The SN54SC4T02-SEP contains four independent 2-input NOR Gates with extended voltage operation to allow for level translation. Each gate performs the Boolean function Y = A + B in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.2-V, 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). Additionally, the 5-V tolerant input pins enable down translation (for example 3.3 V to 2.5 V output).