2 Setup and Configuration

TXE81XX SPI to GPIO expander family is controlled through the 4-wire SPI interface: MISO (master-in-slave-out), MOSI (master-out-slave-in), SCLK (clock), and CS (chip select) lines. To this day, the terminology has since been redefined to the following.

MISO → POCI (peripheral-out-controller-in)

MOSI → PICO (peripheral-in-controller-out)

SCLK is the same

CS is the same

The TXE81XX follows the terminology as follows.

SDI (serial-data-input) → MOSI / PICO

SDO (serial-data-output) → MISO / POCI

SCLK → Clock

CS → Chip Select

In this example, the M0 launchpad LP-MSPM0C1104 is used to program the TXE8124 with the following connections.

VCC = 3.3V → (pin 2)

PA11 → SCLK (pin 29)

PA16 → MISO/POCI/SDO (pin 1)

PA18 → MOSI/PICO/SDI (pin 30)

PA2 → /CS (pin 28)

GND → (pin 3)

The SPI settings are set for 500kHz SPI clock, CPOL (clock idle polarity) = 0 (LOW), CPHA (clock-phase) = 0 (rising-edge / leading edge).

Figure 2-1 is the complete block diagram used for the physical connections between the TXE8124 and the MSPM0.