SBAS426H August   2008  – March 2016 ADS1246 , ADS1247 , ADS1248

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Timing Requirements
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Noise Performance
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  ADC Input and Multiplexer
      2. 9.3.2  Low-Noise PGA
        1. 9.3.2.1 PGA Common-Mode Voltage Requirements
        2. 9.3.2.2 PGA Common-Mode Voltage Calculation Example
        3. 9.3.2.3 Analog Input Impedance
      3. 9.3.3  Clock Source
      4. 9.3.4  Modulator
      5. 9.3.5  Digital Filter
      6. 9.3.6  Voltage Reference Input
      7. 9.3.7  Internal Voltage Reference
      8. 9.3.8  Excitation Current Sources
      9. 9.3.9  Sensor Detection
      10. 9.3.10 Bias Voltage Generation
      11. 9.3.11 General-Purpose Digital I/O
      12. 9.3.12 System Monitor
        1. 9.3.12.1 Power-Supply Monitor
        2. 9.3.12.2 External Voltage Reference Monitor
        3. 9.3.12.3 Ambient Temperature Monitor
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power Up
      2. 9.4.2 Reset
      3. 9.4.3 Power-Down Mode
      4. 9.4.4 Conversion Control
        1. 9.4.4.1 Settling Time for Channel Multiplexing
        2. 9.4.4.2 Channel Cycling and Overload Recovery
        3. 9.4.4.3 Single-Cycle Settling
        4. 9.4.4.4 Digital Filter Reset Operation
      5. 9.4.5 Calibration
        1. 9.4.5.1 Offset Calibration Register: OFC[2:0]
        2. 9.4.5.2 Full-Scale Calibration Register: FSC[2:0]
        3. 9.4.5.3 Calibration Commands
          1. 9.4.5.3.1 System Offset and Self Offset Calibration
          2. 9.4.5.3.2 System Gain Calibration
        4. 9.4.5.4 Calibration Timing
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Chip Select (CS)
        2. 9.5.1.2 Serial Clock (SCLK)
        3. 9.5.1.3 Data Input (DIN)
        4. 9.5.1.4 Data Ready (DRDY)
        5. 9.5.1.5 Data Output and Data Ready (DOUT/DRDY)
        6. 9.5.1.6 SPI Reset
        7. 9.5.1.7 SPI Communication During Power-Down Mode
      2. 9.5.2 Data Format
      3. 9.5.3 Commands
        1. 9.5.3.1  WAKEUP (0000 000x)
        2. 9.5.3.2  SLEEP (0000 001x)
        3. 9.5.3.3  SYNC (0000 010x)
        4. 9.5.3.4  RESET (0000 011X)
        5. 9.5.3.5  RDATA (0001 001x)
        6. 9.5.3.6  RDATAC (0001 010x)
        7. 9.5.3.7  SDATAC (0001 011x)
        8. 9.5.3.8  RREG (0010 rrrr, 0000 nnnn)
        9. 9.5.3.9  WREG (0100 rrrr, 0000 nnnn)
        10. 9.5.3.10 SYSOCAL (0110 0000)
        11. 9.5.3.11 SYSGCAL (0110 0001)
        12. 9.5.3.12 SELFOCAL (0110 0010)
        13. 9.5.3.13 NOP (1111 1111)
        14. 9.5.3.14 Restricted Command (1111 0001)
    6. 9.6 Register Maps
      1. 9.6.1 ADS1246 Register Map
      2. 9.6.2 ADS1246 Detailed Register Definitions
        1. 9.6.2.1 BCS—Burn-out Current Source Register (offset = 00h) [reset = 01h]
        2. 9.6.2.2 VBIAS—Bias Voltage Register (offset = 01h) [reset = 00h]
        3. 9.6.2.3 MUX—Multiplexer Control Register (offset = 02h) [reset = x0h]
        4. 9.6.2.4 SYS0—System Control Register 0 (offset = 03h) [reset = 00h]
        5. 9.6.2.5 OFC—Offset Calibration Coefficient Registers (offset = 04h, 05h, 06h) [reset = 00h, 00h, 00h]
        6. 9.6.2.6 FSC—Full-Scale Calibration Coefficient Registers (offset = 07h, 08h, 09h) [reset = PGA dependent]
        7. 9.6.2.7 ID—ID Register (offset = 0Ah) [reset = x0h]
      3. 9.6.3 ADS1247 and ADS1248 Register Map
      4. 9.6.4 ADS1247 and ADS1248 Detailed Register Definitions
        1. 9.6.4.1  MUX0—Multiplexer Control Register 0 (offset = 00h) [reset = 01h]
        2. 9.6.4.2  VBIAS—Bias Voltage Register (offset = 01h) [reset = 00h]
        3. 9.6.4.3  MUX1—Multiplexer Control Register 1 (offset = 02h) [reset = x0h]
        4. 9.6.4.4  SYS0—System Control Register 0 (offset = 03h) [reset = 00h]
        5. 9.6.4.5  OFC—Offset Calibration Coefficient Register (offset = 04h, 05h, 06h) [reset = 00h, 00h, 00h]
        6. 9.6.4.6  FSC—Full-Scale Calibration Coefficient Register (offset = 07h, 08h, 09h) [reset = PGA dependent]
        7. 9.6.4.7  IDAC0—IDAC Control Register 0 (offset = 0Ah) [reset = x0h]
        8. 9.6.4.8  IDAC1—IDAC Control Register 1 (offset = 0Bh) [reset = FFh]
        9. 9.6.4.9  GPIOCFG—GPIO Configuration Register (offset = 0Ch) [reset = 00h]
        10. 9.6.4.10 GPIODIR—GPIO Direction Register (offset = 0Dh) [reset = 00h]
        11. 9.6.4.11 GPIODAT—GPIO Data Register (offset = 0Eh) [reset = 00h]
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Serial Interface Connections
      2. 10.1.2 Analog Input Filtering
      3. 10.1.3 External Reference and Ratiometric Measurements
      4. 10.1.4 Establishing a Proper Common-Mode Input Voltage
      5. 10.1.5 Isolated (or Floating) Sensor Inputs
      6. 10.1.6 Unused Inputs and Outputs
      7. 10.1.7 Pseudo Code Example
      8. 10.1.8 Channel Multiplexing Example
      9. 10.1.9 Power-Down Mode Example
    2. 10.2 Typical Applications
      1. 10.2.1 Ratiometric 3-Wire RTD Measurement System
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Topology
          2. 10.2.1.2.2 RTD Selection
          3. 10.2.1.2.3 Excitation Current
          4. 10.2.1.2.4 Reference Resistor RREF
          5. 10.2.1.2.5 PGA Setting
          6. 10.2.1.2.6 Common-Mode Input Range
          7. 10.2.1.2.7 Input and Reference Low-Pass Filters
          8. 10.2.1.2.8 Register Settings
        3. 10.2.1.3 Application Curves
      2. 10.2.2 K-Type Thermocouple Measurement (-200°C to +1250°C) with Cold-Junction Compensation
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Biasing Resistors
          2. 10.2.2.2.2 Input Filtering
          3. 10.2.2.2.3 PGA Setting
          4. 10.2.2.2.4 Cold-Junction Measurement
          5. 10.2.2.2.5 Calculated Resolution
          6. 10.2.2.2.6 Register Settings
    3. 10.3 Do's and Don'ts
  11. 11Power-Supply Recommendations
    1. 11.1 Power-Supply Sequencing
    2. 11.2 Power-Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

9 Detailed Description

9.1 Overview

The ADS1246, ADS1247 and ADS1248 devices are highly integrated 24-bit data converters. The devices include a low-noise, high-input impedance programmable gain amplifier (PGA), a delta-sigma (ΔΣ) ADC with an adjustable single-cycle settling digital filter, internal oscillator, and an SPI-compatible serial interface.

The ADS1247 and ADS1248 also include a flexible input multiplexer with system monitoring capability and general-purpose I/O settings, a very low-drift voltage reference, and two matched current sources for sensor excitation. Figure 49 and Figure 50 show the various functions incorporated in each device.

9.2 Functional Block Diagram

ADS1246 ADS1247 ADS1248 ai_46_fbd_new_sbas426.gif Figure 49. ADS1246 Block Diagram
ADS1246 ADS1247 ADS1248 ai_47_48_fbd_new_sbas426.gif Figure 50. ADS1247, ADS1248 Block Diagram

9.3 Feature Description

9.3.1 ADC Input and Multiplexer

The ADC measures the input signal through the onboard PGA. All analog inputs are connected to the internal AINP or AINN analog inputs through the analog multiplexer. Figure 51 shows a block diagram of the analog input multiplexer.

The input multiplexer connects to eight (ADS1248) or four (ADS1247) analog inputs. Any analog input pin can be selected as the positive input or negative input through the MUX0 register, while the ADS1246 has AINP and AINN connections for a single differential channel. The multiplexer also allows the on-chip excitation current and bias voltage to be selected to a specific channel.

Through the input multiplexer, the ambient temperature (internal temperature sensor), AVDD, DVDD, and external reference are all selectable for measurement. See System Monitor for details.

On the ADS1247 and ADS1248, the analog inputs can also be configured as general-purpose inputs and outputs (GPIOs). See General-Purpose Digital I/O for more details.

ADS1246 ADS1247 ADS1248 ai_input_mux_bas426.gif Figure 51. Analog Input Multiplexer Circuit

ESD diodes protect the ADC inputs. To prevent these diodes from turning on, make sure the voltages on the analog input pins do not drop below AVSS by more than 100 mV, and do not exceed AVDD by more than 100 mV, as shown in Equation 2. The same caution is true if the inputs are configured to be GPIOs.

Equation 2. AVSS – 100 mV < V(AINX) < AVDD + 100 mV

9.3.2 Low-Noise PGA

The ADS1246, ADS1247, and ADS1248 feature a low-drift, low-noise, high input impedance programmable gain amplifier (PGA). The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128 by register SYS0. Figure 52 shows a simplified diagram of the PGA.

The PGA consists of two chopper-stabilized amplifiers (A1 and A2) and a resistor feedback network that sets the gain of the PGA. The PGA input is equipped with an electromagnetic interference (EMI) filter, as shown in Figure 52. Note that as with any PGA, ensure that the input voltage stays within the specified common-mode input range. The common-mode input voltage (VCM) must be within the range shown in Equation 3.

Equation 3. ADS1246 ADS1247 ADS1248 q_ai_vcm_range_sbas426.gif
ADS1246 ADS1247 ADS1248 ai_pga_diagram_sbas426.gif Figure 52. Simplified Diagram of the PGA

Gain is changed inside the device using a variable resistor, RG. The differential full-scale input voltage range (FSR) of the PGA is defined by the gain setting and the reference voltage used, as shown in Equation 4.

Equation 4. FSR = ±VREF / Gain

Table 7 shows the corresponding full-scale input ranges when using the internal 2.048-V reference.

Table 7. PGA Full-Scale Range

PGA GAIN SETTING FSR
1 ±2.048 V
2 ±1.024 V
4 ±0.512 V
8 ±0.256 V
16 ±0.128 V
32 ±0.064 V
64 ±0.032 V
128 ±0.016 V

9.3.2.1 PGA Common-Mode Voltage Requirements

To stay within the linear operating range of the PGA, the input signals must meet certain requirements that are discussed in this section.

The outputs of both amplifiers (A1 and A2) in Figure 52 can not swing closer to the supplies (AVSS and AVDD) than 100 mV. If the outputs OUTP and OUTN are driven to within 100 mV of the supply rails, the amplifiers saturate and consequently become nonlinear. To prevent this nonlinear operating condition, the output voltages must meet Equation 5.

Equation 5. AVSS + 0.1 V ≤ V(OUTN), V(OUTP) ≤ AVDD – 0.1 V

Translating the requirements of Equation 5 into requirements referred to the PGA inputs (AINP and AINN) is beneficial because there is no direct access to the outputs of the PGA. The PGA employs a symmetrical design; therefore, the common-mode voltage at the output of the PGA can be assumed to be the same as the common-mode voltage of the input signal, as shown in Figure 53.

ADS1246 ADS1247 ADS1248 pga_cmvr_sbas426.gif Figure 53. PGA Common-Mode Voltage

The common-mode voltage is calculated using Equation 6.

Equation 6. VCM = ½ (V(AINP) + V(AINN)) = ½ (V(OUTP) + V(OUTN))

The voltages at the PGA inputs (AINP and AINN) can be expressed as Equation 7 and Equation 8.

Equation 7. V(AINP) = VCM + ½ VIN
Equation 8. V(AINN) = VCM – ½ VIN

The output voltages (V(OUTP) and V(OUTN)) can then be calculated as Equation 9 and Equation 10.

Equation 9. V(OUTP) = VCM + ½ Gain · VIN
Equation 10. V(OUTN) = VCM – ½ Gain · VIN

The requirements for the output voltages of amplifiers A1 and A2 (Equation 5) can now be translated into requirements for the input common-mode voltage range using Equation 9 and Equation 10, which are given in Equation 11 and Equation 12.

Equation 11. VCM (MIN) ≥ AVSS + 0.1 V + ½ Gain · VIN (MAX)
Equation 12. VCM (MAX) ≤ AVDD – 0.1 V – ½ Gain · VIN (MAX)

To calculate the minimum and maximum common-mode voltage limits, the maximum differential input voltage (VIN (MAX)) that occurs in the application must be used. VIN (MAX) can be less than the maximum possible full-scale value.

9.3.2.2 PGA Common-Mode Voltage Calculation Example

The following paragraphs explain how to apply Equation 11 and Equation 12 to a hypothetical application. The setup for this example is AVDD = 3.3 V, AVSS = 0 V, and gain = 16, using an external reference, VREF = 2.5 V. The maximum possible differential input voltage VIN = (V(AINP) – V(AINN)) that can be applied is then limited to the full-scale range of FSR = ±2.5 V / 16 = ±0.156 V. Consequently, Equation 11 and Equation 12 yield an allowed VCM range of 1.35 V ≤ VCM ≤ 1.95 V.

If the sensor signal connected to the inputs in this hypothetical application does not make use of the entire full-scale range but is limited to VIN (MAX) = ±0.1 V, for example, then this reduced input signal amplitude relaxes the VCM restriction to 0.9 V ≤ VCM ≤ 2.4 V.

In the case of a fully-differential sensor signal, each input (AINP, AINN) can swing up to ±50 mV around the common-mode voltage (V(AINP) + V(AINN)) / 2, which must remain between the limits of 0.9 V and 2.4 V. The output of a symmetrical wheatstone bridge is an example of a fully-differential signal. Figure 54 shows a situation where the common-mode voltage of the input signal is at the lowest limit. V(OUTN) is exactly at 0.1 V in this case. Any further decrease in common-mode voltage (VCM) or increase in differential input voltage (VIN) drives V(OUTN) below 0.1 V and saturates amplifier A2.

ADS1246 ADS1247 ADS1248 pga_example_sbas426.gif Figure 54. Example where VCM is at Lowest Limit

In contrast, the signal of an RTD is of a pseudo-differential nature (if implemented as shown in one of the application example sections, 3-Wire RTD Measurement), where the negative input is held at a constant voltage other than 0 V and only the voltage on the positive input changes. When a pseudo-differential signal must be measured, the negative input in this example must be biased at a voltage from 0.85 V to 2.35 V. The positive input can then swing up to VIN (MAX) = 100 mV above the negative input. In this case, the common-mode voltage changes at the same time the voltage on the positive input changes. That is, while the input signal swings between 0 V ≤ VIN ≤ VIN (MAX), the common-mode voltage swings between V(AINN) ≤ VCM ≤ V(AINN) + ½ VIN (MAX). Satisfying the common-mode voltage requirements for the maximum input voltage VIN (MAX) ensures the requirements are met throughout the entire signal range.

Figure 55 and Figure 56 show examples of both fully-differential and pseudo-differential signals, respectively.

ADS1246 ADS1247 ADS1248 VCM_FullyDifferential_bas501.gif Figure 55. Fully-Differential Input Signal
ADS1246 ADS1247 ADS1248 VCM_PseudoDifferential_bas501.gif Figure 56. Pseudo-Differential Input Signal

NOTE

With a unipolar power supply, the input range does not extend to the ground. Equation 11 and Equation 12 show the common-mode voltage requirements.

  • VCM (MIN) ≥ AVSS + 0.1 V + ½ Gain · VIN (MAX)
  • VCM (MAX) ≤ AVDD – 0.1 V – ½ Gain · VIN (MAX)

9.3.2.3 Analog Input Impedance

The device inputs are buffered through a high-input impedance PGA before they reach the ΔΣ modulator. For the majority of applications, the input current is minimal and can be neglected. However, because the PGA is chopper-stabilized for noise and offset performance, the input impedance is best described as a small absolute input current. The absolute input current for selected channels is approximately proportional to the selected modulator clock. Table 8 shows the typical values for these currents with a differential voltage coefficient and the corresponding input impedances over data rate.

Table 8. Typical Values for Analog Input Current over Data Rate(1)

CONDITION ABSOLUTE INPUT CURRENT EFFECTIVE INPUT IMPEDANCE
DR = 5 SPS, 10 SPS, 20 SPS ± (0.5 nA + 0.1 nA/V) 5000 MΩ
DR = 40 SPS, 80 SPS, 160 SPS ± (2 nA + 0.5 nA/V) 1200 MΩ
DR = 320 SPS, 640 SPS, 1 kSPS ± (4 nA + 1 nA/V) 600 MΩ
DR = 2 kSPS ± (8 nA + 2 nA/V) 300 MΩ
(1) Input current with VCM = 2.5 V. TA = 25°C, AVDD = 5 V, and AVSS = 0 V.

9.3.3 Clock Source

The device can use either the internal oscillator or an external clock. Connect the CLK pin to DGND before power up or reset to activate the internal oscillator. Connecting an external clock to the CLK pin at any time deactivates the internal oscillator, with the device then operating on the external clock. After the device switches to the external clock, it cannot be switched back to the internal oscillator without cycling the power supplies or resetting the device.

9.3.4 Modulator

A third-order delta-sigma modulator is used in the ADS1246, ADS1247, and ADS1248 devices. The modulator converts the analog input voltage into a pulse code modulated (PCM) data stream. To save power, the modulator clock runs from 32 kHz up to 512 kHz for different data rates, as shown in Table 9.

Table 9. Modulator Clock Frequency for Different Data Rates

DATA RATE
(SPS)
MODULATOR RATE (fMOD)(1)
(kHz)
fCLK/fMOD
5, 10, 20 32 128
40, 80, 160 128 32
320, 640, 1000 256 16
2000 512 8
(1) Using the internal oscillator or an external 4.096-MHz clock.

9.3.5 Digital Filter

The ADC uses linear-phase finite impulse response (FIR) digital filters that can be adjusted for different output data rates. The digital filter always settles in a single cycle.

Table 10 shows the exact data rates when an external clock equal to 4.096 MHz is used. Also shown is the signal –3-dB bandwidth, and the 50-Hz and 60-Hz attenuation. For good 50-Hz or 60-Hz rejection, use a data rate of 20 SPS or slower.

The frequency responses of the digital filter are shown in Figure 57 to Figure 67. Figure 60 illustrates a detailed view of the filter frequency response from 48 Hz to 62 Hz for a 20-SPS data rate. All filter plots are generated with a 4.096-MHz external clock.

Data rates and digital filter frequency responses scale proportionally with changes in the system clock frequency. The internal oscillator frequency has a variation, as specified in Electrical Characteristics that will also affect data rates and the digital filter frequency response.

Table 10. Digital Filter Specifications(1)

NOMINAL DATA RATE ACTUAL DATA RATE –3-dB BANDWIDTH ATTENUATION
fIN = 50 Hz ±0.3 Hz fIN = 60 Hz ±0.3 Hz fIN = 50 Hz ±1 Hz fIN = 60 Hz ±1 Hz
5 SPS 5.018 SPS 2.26 Hz –106 dB –74 dB –81 dB –69 dB
10 SPS 10.037 SPS 4.76 Hz –106 dB –74 dB –80 dB –69 dB
20 SPS 20.075 SPS 14.8 Hz –71 dB –74 dB –66 dB –68 dB
40 SPS 40.15 SPS 9.03 Hz
80 SPS 80.301 SPS 19.8 Hz
160 SPS 160.6 SPS 118 Hz
320 SPS 321.608 SPS 154 Hz
640 SPS 643.21 SPS 495 Hz
1000 SPS 1000 SPS 732 Hz
2000 SPS 2000 SPS 1465 Hz
(1) Values shown for fCLK = 4.096 MHz.

space

ADS1246 ADS1247 ADS1248 ai_filter_5sps_bas426.gif Figure 57. Filter Profile with Data Rate = 5 SPS
ADS1246 ADS1247 ADS1248 ai_filter_20sps_bas426.gif Figure 59. Filter Profile with Data Rate = 20 SPS
ADS1246 ADS1247 ADS1248 ai_filter_40sps_bas426.gif Figure 61. Filter Profile with Data Rate = 40 SPS
ADS1246 ADS1247 ADS1248 ai_filter_160sps_bas426.gif Figure 63. Filter Profile with Data Rate = 160 SPS
ADS1246 ADS1247 ADS1248 ai_filter_640sps_bas426.gif Figure 65. Filter Profile with Data Rate = 640 SPS
ADS1246 ADS1247 ADS1248 ai_filter_2ksps_bas426.gif Figure 67. Filter Profile with Data Rate = 2 kSPS
ADS1246 ADS1247 ADS1248 ai_filter_10sps_bas426.gif Figure 58. Filter Profile with Data Rate = 10 SPS
ADS1246 ADS1247 ADS1248 ai_filter_20_zoom_bas426.gif Figure 60. Detailed View of Filter Profile with Data Rate = 20 SPS Between 48 Hz and 62 Hz
ADS1246 ADS1247 ADS1248 ai_filter_80sps_bas426.gif Figure 62. Filter Profile with Data Rate = 80 SPS
ADS1246 ADS1247 ADS1248 ai_filter_320sps_bas426.gif Figure 64. Filter Profile with Data Rate = 320 SPS
ADS1246 ADS1247 ADS1248 ai_filter_1ksps_bas426.gif Figure 66. Filter Profile with Data Rate = 1 kSPS

9.3.6 Voltage Reference Input

The voltage reference for the device is the differential voltage between REFP and REFN, given by Equation 13:

Equation 13. VREF = V(REFP) – V(REFN)

In the case of the ADS1246, these pins are dedicated inputs. For the ADS1247 and ADS1248, there is a multiplexer that selects the reference inputs, as shown in Figure 68. The reference input uses a buffer to increase the input impedance.

As with the analog inputs, REFP0 and REFN0 can be configured as digital I/Os on the ADS1247 and ADS1248.

ADS1246 ADS1247 ADS1248 ai_ref_in_mux_bas426.gif Figure 68. Reference Input Multiplexer

The reference input circuit has ESD diodes to protect the inputs. To prevent the diodes from turning on, make sure the voltage on the reference input pin is not less than AVSS – 100 mV, and does not exceed AVDD + 100 mV, as shown in Equation 14.

Equation 14. AVSS – 100 mV < (V(REFP) or V(REFN)) < AVDD + 100 mV

9.3.7 Internal Voltage Reference

The ADS1247 and ADS1248 have an internal voltage reference with a low temperature coefficient. The output of the voltage reference is 2.048 V (nominal) with the capability of both sourcing and sinking up to 10 mA of current.

The voltage reference must have a capacitor connected between VREFOUT and VREFCOM. The value of the capacitance must be in the range of 1 μF to 47 μF. Large values provide more noise filtering of the reference; however, the turnon time increases with capacitance, as shown in Table 11. For stability reasons, VREFCOM must have a path with an impedance less than 10 Ω to AC ground nodes, such as GND (for a 0-V to 5-V analog power supply), or AVSS (for a ±2.5-V analog power supply). In case this impedance is higher than 10 Ω, connect a capacitor of at least 0.1 μF between VREFCOM and an AC ground node (for example, GND).

NOTE

Because time is required for the voltage reference to settle to the final voltage, take care when the device is turned off between conversions. Allow adequate time for the internal reference to fully settle before starting a new conversion.

Table 11. Internal Reference Settling Time

VREFOUT CAPACITOR SETTLING ERROR TIME TO REACH THE SETTLING ERROR
1 μF ±0.5% 70 μs
±0.1% 110 μs
4.7 μF ±0.5% 290 μs
±0.1% 375 μs
47 μF ±0.5% 2.2 ms
±0.1% 2.4 ms

The internal reference is controlled by the MUX1 register; by default, the internal reference is off after power up (see ADS1247 and ADS1248 Detailed Register Definitions for more details). Therefore, the internal reference must first be turned on and then connected through the internal reference multiplexer. Because the internal reference is used to generate the current reference for the excitation current sources, it must be turned on before the excitation currents become available.

9.3.8 Excitation Current Sources

The ADS1247 and ADS1248 provide two matched excitation current sources (IDACs) for RTD applications. For three-wire RTD applications, the matched current sources can be used to cancel the errors caused by sensor lead resistance. The output current of the IDACs can be programmed to 50 μA, 100 μA, 250 μA,
500 μA, 750 μA, 1000 μA, or 1500 μA.

The two matched current sources can be connected to dedicated current output pins IEXC1 and IEXC2 (ADS1248 only), or to any analog input pin (ADS1247 and ADS1248); see ADS1247 and ADS1248 Detailed Register Definitions for more information. Both current sources can be connected to the same pin. The internal reference must be turned on and the proper amount of capacitance applied to VREFOUT when using the excitation current sources.

9.3.9 Sensor Detection

To help detect a possible sensor malfunction, the device provides selectable current sources (0.5 μA, 2 μA, or
10 μA) to act as burn-out current sources. When enabled, one current source sources current to the selected positive analog input (AINP) while the other current source sinks current from the selected negative analog input (AINN).

In case of an open circuit in the sensor, these burn-out current sources pull the positive input towards AVDD and the negative input towards AVSS, resulting in a full-scale reading. A full-scale reading may also indicate that the sensor is overloaded or that the reference voltage is absent. A near-zero reading may indicate a shorted sensor. The absolute value of the burn-out current sources typically varies by ±10% and the internal multiplexer adds a small series resistance. Therefore, distinguishing a shorted sensor condition from a normal reading can be difficult, especially if an RC filter is used at the inputs. In other words, even if the sensor is shorted, the voltage drop across the external filter resistance and the residual resistance of the multiplexer causes the output to read a value higher than zero.

The ADC readings of a functional sensor may be corrupted when the burn-out current sources are enabled. TI recommends disabling the burn-out current sources when performing the precision measurement, and only enabling them to test for sensor fault conditions.

9.3.10 Bias Voltage Generation

A selectable bias voltage is provided for use with unbiased thermocouples. The bias voltage is (AVDD + AVSS) / 2 and can be applied to any analog input channel through the internal input multiplexer. The bias voltage turnon times for different sensor capacitances are listed in Table 12.

The internal bias voltage generator, when selected on multiple channels, causes them to be internally shorted. Because of this, take care to limit the amount of current that may flow through the device. TI recommends that under no circumstances should more than 5 mA be allowed to flow through this path. This applies when the device is in operation and when it is powered down.

Table 12. Bias Voltage Settling Time

SENSOR CAPACITANCE SETTLING TIME
0.1 μF 220 μs
1 μF 2.2 ms
10 μF 22 ms
200 μF 450 ms

9.3.11 General-Purpose Digital I/O

The ADS1248 has eight pins and the ADS1247 has four pins that serve a dual purpose as either analog inputs or general-purpose digital inputs and outputs (GPIOs).

Three registers control the function of the GPIO pins. Use the GPIO configuration register (IOCFG) to enable a pin as a GPIO pin. The GPIO direction register (IODIR) configures the GPIO pin as either an input or an output. Finally, the GPIO data register (IODAT) contains the GPIO data. If a GPIO pin is configured as an input, the respective IODAT[x] bit reads the status of the pin; if a GPIO pin is configured as an output, write the output status to the respective IODAT[x] bit. For more information about the use of GPIO pins, please see the ADS1247 and ADS1248 Detailed Register Definitions section.

Figure 69 shows a diagram of how these functions are combined onto a single pin. Note that when the pin is configured as a GPIO, the corresponding logic is powered from AVDD and AVSS. When the ADS1247 and ADS1248 are operated with bipolar analog supplies, the GPIO outputs bipolar voltages. Care must be taken loading the GPIO pins when used as outputs because large currents can cause droop or noise on the analog supplies.

ADS1246 ADS1247 ADS1248 ai_ana_dig_int_pin_bas426.gif Figure 69. Analog and Data Interface Pin

9.3.12 System Monitor

The ADS1247 and ADS1248 provide a system monitor function. This function can measure the analog power supply, digital power supply, external voltage reference, or ambient temperature. Note that the system monitor function provides a coarse result. When the system monitor is enabled, the analog inputs are disconnected.

9.3.12.1 Power-Supply Monitor

The system monitor can measure the analog or digital power supply. When measuring the power supply (VSP), the resulting conversion is approximately 1/4 of the actual power supply voltage, as shown in Equation 15.

Equation 15. Conversion Result = (VSP / 4) / VREF

9.3.12.2 External Voltage Reference Monitor

The ADC can measure the external voltage reference. In this configuration, the monitored external voltage reference (VREX) is connected to the analog input. The result (conversion code) is approximately 1/4 of the actual reference voltage, as shown in Equation 16.

Equation 16. Conversion Result = (VREX / 4) / VREF

NOTE

The internal reference voltage must be enabled when measuring an external voltage reference using the system monitor.

9.3.12.3 Ambient Temperature Monitor

On-chip diodes provide temperature-sensing capability. When selecting the temperature monitor function, the anodes of two diodes are connected to the ADC. Typically, the difference in diode voltage is 118 mV at
TA = 25°C with a temperature coefficient of 405 μV/°C.

9.4 Device Functional Modes

9.4.1 Power Up

When DVDD is powered up, the internal power-on reset module generates a pulse that resets all digital circuitry. All the digital circuits are held in a reset state for 216 system clocks to allow the analog circuits and the internal digital power supply to settle. SPI communication cannot occur until the internal reset is released.

9.4.2 Reset

When the RESET pin goes low, the device is immediately reset. All registers are restored to default values. The device stays in reset mode as long as the RESET pin stays low. When the RESET pin goes high, the ADC comes out of reset mode and is able to convert data. After the RESET pin goes high, and when the system clock frequency is 4.096 MHz, the digital filter and the registers are held in a reset state for 0.6 ms when
fCLK = 4.096 MHz. Therefore, valid SPI communication can only be resumed 0.6 ms after the RESET pin goes high; see Figure 4. When the RESET pin goes low, the clock selection is reset to the internal oscillator.

A reset can also be performed by the RESET command through the serial interface and is functionally the same as using the RESET pin. For information about using the RESET command, see RESET (0000 011X).

9.4.3 Power-Down Mode

Power consumption is reduced to a minimum by placing the device into power-down mode. There are two ways to put the device into power-down mode: using the SLEEP command and taking the START pin low.

During power-down mode, the internal reference status depends on the setting of the VREFCON bits in the MUX1 register; see Register Maps for details.

9.4.4 Conversion Control

The START pin provides precise control of conversions. Pulse the START pin high to begin a conversion, as shown in Figure 70 and Table 13. The conversion completion is indicated by the DRDY pin going low and with the DOUT/DRDY pin when the DRDY MODE bit is 1 in the IDAC0 register. When the conversion completes, the device automatically powers down. During power down, the conversion result can be retrieved; however, START must be taken high before communicating with the configuration registers. The device stays powered down until the START pin is returned high to begin a new conversion. When the START pin is returned high, the decimation filter is held in a reset state for 32 modulator clock cycles internally to allow the analog circuits to settle.

Holding the START pin high will configure the device to continuously convert as shown in Figure 71.

ADS1246 ADS1247 ADS1248 ai_spi_start_single_conv_sbas426.gif Figure 70. Timing for Single Conversion Using the Start Pin

Table 13. Start Pin Conversion Times for Figure 70(1)

SYMBOL DESCRIPTION DATA RATE (SPS) VALUE UNIT
tCONV Time from the START rising edge to DRDY and DOUT/DRDY going low 5 200.295 ms
10 100.644 ms
20 50.825 ms
40 25.169 ms
80 12.716 ms
160 6.489 ms
320 3.247 ms
640 1.692 ms
1000 1.138 ms
2000 0.575 ms
(1) For fCLK = 4.096MHz
ADS1246 ADS1247 ADS1248 ai_tim_start_high_bas426.gif
NOTE: SCLK held low in this example.
Figure 71. Timing for Conversion With Start Pin High

With the START pin held high, the ADC converts the selected input channels continuously. This configuration continues until the START pin is taken low. The START pin can also be used to perform synchronized measurements for multi-channel applications by pulsing the START pin. With multiple devices, if each device receives the START pin pulse at the same time, all devices start a conversion on the rise of the start pin. If all devices are operating with the same data rate, all of the devices complete the conversion at the same time.

Conversions can also be initiated through SPI commands as well. Similar to using the START pin, the device can be put into a power-down mode using the SLEEP command. Functionally, this is similar to taking the START pin low. To initiate a conversion, the WAKEUP command powers up the ADC and starts a conversion, similar to returning the START pin high. Note that the START pin must be held high to use commands to control conversions. Do not combine using the START pin and using commands to control conversions.

Also, sending a SYNC command immediately starts a new ADC conversion. For the SYNC command, the digital filter is reset, starting a new conversion without completing the previous conversion. This is useful in synchronizing conversions from multiple devices or maintaining periodic timing from multiple channels.

Similarly, writing to any of the first four registers (MUX0, VBIAS, MUX1, or SYS0; addresses 00h to 04h) automatically resets the digital filter. A change in any of these registers makes the appropriate setup change in the device, but also restarts the conversion similar to a SYNC command.

9.4.4.1 Settling Time for Channel Multiplexing

The device is a true single-cycle settling ΔΣ converter. The first data available after the start of a conversion are fully settled and valid for use, provided that the input signal has settled to its final result. The time required to settle is roughly equal to the inverse of the data rate. The exact time depends on the specific data rate and the operation that resulted in the start of a conversion; see Table 14 for specific values.

9.4.4.2 Channel Cycling and Overload Recovery

When cycling through channels, take care when configuring the device to ensure that settling occurs within one cycle. For setups that cycle through MUX channels, but do not change PGA and data rate settings, changing the MUX0 register is sufficient. However, when changing PGA and data rate settings, ensure that an overloaded condition cannot occur during the transmission. When configuration register data are transferred to the device, new settings become active at the end of each register byte sent. Therefore, a brief overload condition can occur during the transmission of configuration data after the completion of the MUX0 byte and before completion of the SYS0 byte. This temporary overload can result in intermittent incorrect readings. To ensure that an overload does not occur, it may be necessary to split the communication into two separate communications allowing the change of the SYS0 register before the change of the MUX0 register.

In the event of an overloaded state, take care to ensure single-cycle settling into the next cycle. Because the device implements a chopper-stabilized PGA, changing data rates during an overload state can cause the chopper to become unstable. This instability results in slow settling time. To prevent this slow settling, always change the PGA setting or MUX setting to a non-overloaded state before changing the data rate.

9.4.4.3 Single-Cycle Settling

The ADS1246, ADS1247, and ADS1248 are capable of single-cycle settling across all gains and data rates. However, to achieve single-cycle settling at 2 kSPS, special care must be taken with respect to the interface using WREG to change a configuration register. When operating at 2 kSPS, the SCLK period must not exceed 520 ns, and the time between the beginning of writing a register byte data and the beginning of a subsequent register byte data must not exceed 4.2 µs. Additionally, when performing multiple individual write commands to the first four registers, wait at least 64 system clocks before initiating another write command.

9.4.4.4 Digital Filter Reset Operation

Apart from the RESET command and the RESET pin, the digital filter is reset automatically when either a write operation to the MUX0, VBIAS, MUX1, or SYS0 registers is performed, when a SYNC command is issued, or the START pin is taken high.

The filter is reset four system clocks (tCLK) after the falling edge of the seventh SCLK of the SYNC command. Similarly, if any write operation takes place in the MUX0 register, regardless of whether the register value changed or not, the filter is reset after the completion of the MUX0 write.

If any write activity takes place in the VBIAS, MUX1, or SYS0 registers, regardless of whether the register value changed or not, the filter is reset. The reset pulse lasts for 32 modulator clocks after the completion of the write operation. If there are multiple write operations, the resulting reset pulse may be viewed as the ANDed result of the different active low pulses created individually by each action.

Table 14 shows the conversion time after a filter reset. Note that this time depends on the operation initiating the reset. Also, the first conversion after a filter reset has a slightly different time than the second and subsequent conversions.

Table 14. Data Conversion Time

NOMINAL DATA RATE (SPS) EXACT DATA RATE
(SPS)
FIRST DATA CONVERSION TIME AFTER FILTER RESET SECOND AND SUBSEQUENT CONVERSION TIME AFTER FILTER RESET
SYNC COMMAND, MUX0 REGISTER WRITE HARDWARE RESET, RESET COMMAND, START PIN HIGH, WAKEUP COMMAND, VBIAS, MUX1, or SYS0 REGISTER WRITE
(ms)(1) NO. OF SYSTEM CLOCK CYCLES (ms)(1) NO. OF SYSTEM CLOCK CYCLES (ms)(1) NO. OF SYSTEM CLOCK CYCLES
5 5.019 199.258 816160 200.26 820265 199.250 816128
10 10.038 99.633 408096 100.635 412201 99.625 408064
20 20.075 49.820 204064 50.822 208169 49.812 204032
40 40.151 24.92 102072 25.172 103106 24.906 102016
80 80.301 12.467 51064 12.719 52098 12.453 51008
160 160.602 6.240 25560 6.492 26594 6.226 25504
320 321.608 3.124 12796 3.25 13314 3.109 12736
640 643.216 1.569 6428 1.695 6946 1.554 6368
1000 1000 1.014 4156 1.141 4674 1 4096
2000 2000 0.514 2108 0.578 2370 0.5 2048
(1) For fCLK = 4.096 MHz.

9.4.5 Calibration

The conversion data are scaled by offset and gain registers before yielding the final output code. As shown in Figure 72, the output of the digital filter is first subtracted by the offset register (OFC) and then multiplied by the full-scale register (FSC) to digitally scale the gain. A digital clipping circuit ensures that the output code does not exceed 24 bits. Equation 17 shows the scaling.

ADS1246 ADS1247 ADS1248 ai_cali_fbd_bas426.gif Figure 72. Calibration Block Diagram
Equation 17. ADS1246 ADS1247 ADS1248 q_final_data_bas426.gif

The values of the offset and full-scale registers are set by writing to them directly, or they are set automatically by calibration commands.

The offset and gain calibration features are intended for correction of minor system level offset and gain errors. When entering manual values into the calibration registers, care must be taken to avoid scaling down the gain register to values far below a scaling factor of 1.0. Under extreme situations it is possible to over-range the ADC. Avoid encountering situations where analog inputs are connected to voltages greater than VREF / gain.

Take care when increasing digital gain with the FSC. When implementing custom digital gains less than 20% higher than nominal and offsets less than 40% of full scale, no special care is required. When operating at digital gains greater than 20% higher than nominal and offsets greater than 40% of full scale, make sure that the offset and gain registers follow the conditions of Equation 18.

Equation 18. ADS1246 ADS1247 ADS1248 q_ai_digital_gain_sbas426.gif

9.4.5.1 Offset Calibration Register: OFC[2:0]

The offset calibration register is a 24-bit word, composed of three 8-bit registers. The offset is in twos complement format with a maximum positive value of 7FFFFFh and a maximum negative value of 800000h. This value is subtracted from the conversion data. A register value of 000000h provides no offset correction. Note that while the offset calibration register value can correct offsets ranging from –FS to +FS (as shown in Table 15), avoid overloading the analog inputs.

Table 15. Final Output Code versus Offset Calibration Register Setting

OFFSET REGISTER FINAL OUTPUT CODE WITH VIN = 0(1)
7FFFFFh 800000h
000001h FFFFFFh
000000h 000000h
FFFFFFh 000001h
800000h 7FFFFFh
(1) Excludes effects of noise and inherent offset errors.

9.4.5.2 Full-Scale Calibration Register: FSC[2:0]

The full-scale or gain calibration register is a 24-bit word composed of three 8-bit registers. The full-scale calibration value is 24-bit, straight binary, normalized to 1.0 at code 400000h. Table 16 summarizes the scaling of the full-scale register. Note that while the full-scale calibration register can correct gain errors > 1 (with gain scaling < 1), make sure to avoid overloading the analog inputs. The default or reset value of FSC depends on the PGA gain setting. A different factory-trimmed FSC reset value is stored for each PGA gain setting which provides gain accuracy over all the device input ranges.

NOTE

The factory-trimmed FSC reset value loads automatically whenever the PGA gain setting changes.

Table 16. Gain Correction Factor versus Full-Scale Calibration Register Setting

FULL-SCALE REGISTER GAIN SCALING
800000h 2.0
400000h 1.0
200000h 0.5
000000h 0

9.4.5.3 Calibration Commands

The device provides commands for three types of calibration: system gain calibration, system offset calibration and self offset calibration. Where absolute accuracy is needed, TI recommends performing a calibration after power up, a change in temperature, a change of gain, and in some cases a change in channel. At the completion of calibration, the DRDY signal goes low indicating the calibration has completed. The first data after calibration are always valid. If the START pin is taken low or a SLEEP command is issued after any calibration command, the device powers down after completing calibration.

After a calibration has started, allow the calibration to complete before issuing any other commands (other than the SLEEP command). Issuing commands during a calibration can result in corrupted data. If this occurs, either resend the calibration command that was aborted or issue a device reset.

9.4.5.3.1 System Offset and Self Offset Calibration

System offset calibration corrects both internal and external offset errors. The system offset calibration is initiated by sending the SYSOCAL command while applying a zero differential input (VIN = 0) to the selected analog inputs while the inputs are within the input common-mode range, ideally at mid-supply.

The self offset calibration is initiated by sending the SELFOCAL command. During self offset calibration, the selected inputs are disconnected from the internal circuitry and a zero differential signal is applied internally, connecting the inputs to mid-supply. With both offset calibrations the offset calibration register (OFC) is updated afterwards. When either offset calibration command is issued, the device stops the current conversion and starts the calibration procedure immediately. An offset calibration should be performed before a gain calibration.

9.4.5.3.2 System Gain Calibration

System gain calibration corrects for gain error in the signal path. The system gain calibration is initiated by sending the SYSGCAL command while applying a full-scale input to the selected analog inputs. Afterwards the full-scale calibration register (FSC) is updated. When a system gain calibration command is issued, the device stops the current conversion and starts the calibration procedure immediately.

9.4.5.4 Calibration Timing

When calibration is initiated, the device performs 16 consecutive data conversions and averages the results to calculate the calibration value. This provides a more accurate calibration value. The time required for calibration is shown in Table 17 and can be calculated using Equation 19:

Equation 19. ADS1246 ADS1247 ADS1248 q_cali_t_sbas426.gif

where

Table 17. Calibration Time Versus Data Rate

DATA RATE
(SPS)
CALIBRATION TIME (tCAL)
(ms)(1)
5 3201.01
10 1601.01
20 801.012
40 400.26
80 200.26
160 100.14
320 50.14
640 25.14
1000 16.14
2000 8.07
(1) For fCLK = 4.096 MHz.

9.5 Programming

9.5.1 Serial Interface

The device provides an SPI-compatible serial communication interface plus a data ready signal (DRDY). Communication is full-duplex with the exception of a few limitations in regards to the RREG command and the RDATA command. These limitations are explained in detail in Commands. For the basic serial interface timing characteristics, see Figure 1 and Figure 2 of this document.

9.5.1.1 Chip Select (CS)

The CS pin activates SPI communication. CS must be low before data transactions and must stay low for the entire SPI communication period. When CS is high, the DOUT/DRDY pin enters a high-impedance state. Therefore, reading and writing to the serial interface are ignored and the serial interface is reset. DRDY pin operation is independent of CS. DRDY will still indicate that a new conversion has completed and is forced high as a response to SCLK, even if CS is high.

Taking CS high deactivates only the SPI communication with the device. Data conversion continues and the DRDY signal can be monitored to check if a new conversion result is ready. A master device monitoring the DRDY signal can select the appropriate slave device by pulling the CS pin low.

9.5.1.2 Serial Clock (SCLK)

SCLK provides the clock for serial communication. SCLK is a Schmitt-trigger input, but TI recommends keeping SCLK as free from noise as possible to prevent glitches from inadvertently shifting the data. Data are shifted into DIN on the falling edge of SCLK and shifted out of DOUT on the rising edge of SCLK.

9.5.1.3 Data Input (DIN)

DIN is used along with SCLK to send data to the device. Data on DIN are shifted into the device on the falling edge of SCLK.

The communication of this device is full-duplex in nature. The device monitors commands shifted in even when data are being shifted out. Data that are present in the output shift register are shifted out when sending in a command. Therefore, make sure that whatever is being sent on the DIN pin is valid when shifting out data. When no command is to be sent to the device when reading out data, send the NOP command on DIN.

9.5.1.4 Data Ready (DRDY)

The DRDY pin goes low to indicate a new conversion is complete, and the conversion result is stored in the conversion result buffer. SCLK must be held low for tDTS after the DRDY low transition (see Figure 2) so that the conversion result is loaded into both the result buffer and the output shift register. Therefore, issue no commands during this time frame if the conversion result is to be read out later. This constraint applies only when CS is asserted and the device is in RDATAC mode. When CS is not asserted, SPI communication with other devices on the SPI bus does not affect loading of the conversion result. After the DRDY pin goes low, it is forced high on the first falling edge of SCLK (so that the DRDY pin can be polled for 0 instead of waiting for a falling edge). If the DRDY pin is not taken high by clocking in SCLKs after it falls low, a short high pulse for a duration of tPWH indicates new data are ready.

9.5.1.5 Data Output and Data Ready (DOUT/DRDY)

The DOUT/DRDY pin has two modes: data out (DOUT) only, or DOUT combined with data ready (DRDY). The DRDY MODE bit determines the function of this pin and can be found in the ID register in the ADS1246 and the IDAC0 register in the ADS1247 and ADS1248. In either mode, the DOUT/DRDY pin goes to a high-impedance state when CS is taken high.

When the DRDY MODE bit is set to 0, this pin functions as DOUT only. Data are clocked out on the rising edge of SCLK, MSB first (as shown in Figure 73).

When the DRDY MODE bit is set to 1, this pin functions as both DOUT and DRDY. Data are shifted out as with DOUT, but the pin adds the DRDY function. Note that this mode will not be operational when the device is in stop read data continuous mode when the SDATAC command is given.

The DRDY MODE bit modifies only the DOUT/DRDY pin functionality. The DRDY pin functionality remains unaffected.

ADS1246 ADS1247 ADS1248 ai_tim_data_ret_dis_bas426.gif
1.

NOINDENT:

CS tied low.
Figure 73. Data Retrieval with the DRDY MODE Bit = 0 (Disabled)

When the DRDY MODE bit is enabled and a new conversion is complete, DOUT/DRDY goes low if it is high. If it is already low, then DOUT/DRDY goes high and then goes low (as shown in Figure 74). Similar to the DRDY pin, a falling edge on the DOUT/DRDY pin signals that a new conversion result is ready. After DOUT/DRDY goes low, the data can be clocked out by providing 24 SCLKs if the device is in read data continuous mode. In order to force DOUT/DRDY high (so that DOUT/DRDY can be polled for a 0 instead of waiting for a falling edge), a no operation command (NOP) or any other command that does not load the data output register can be sent after reading out the data. Because SCLKs can only be sent in multiples of eight, a NOP can be sent to force DOUT/DRDY high if no other command is pending. The DOUT/DRDY pin goes high after the first rising edge of SCLK after reading the conversion result completely (as shown in Figure 75). The same condition also applies after an RREG command. After all the register bits have been read out, the first rising edge of SCLK forces DOUT/DRDY high. Figure 76 shows an example where sending an extra NOP command after reading out a register with an RREG command forces the DOUT/DRDY pin high.

ADS1246 ADS1247 ADS1248 ai_tim_data_ret_drdy_sbas426.gif
1.

NOINDENT:

CS tied low.
Figure 74. Data Retrieval with the DRDY MODE Bit = 1 (Enabled)
ADS1246 ADS1247 ADS1248 ai_tim_dout_drdy_high_sbas426.gif
1.

NOINDENT:

DRDY MODE bit enabled, CS tied low.
Figure 75. DOUT/DRDY Forced High after Retrieving the Conversion Result
ADS1246 ADS1247 ADS1248 ai_tim_dout_drdy_high_rreg_sbas426.gif
1.

NOINDENT:

DRDY MODE bit enabled, CS tied low.
Figure 76. DOUT/DRDY Forced High after Reading Register Data

9.5.1.6 SPI Reset

SPI communication is reset in several ways. To reset the serial interface (without resetting the registers or the digital filter), the CS pin can be pulled high. Taking the RESET pin low resets the serial interface along with all the other digital functions. It will also return all registers to their default values and start a new conversion.

In systems where CS is tied low permanently, register writes must always be fully completed in 8-bit increments. If a glitch on SCLK disrupts SPI communications, commands will not be recognized by the device. The device implements a timeout function for all listed commands in the event that data are corrupted and the CS pin is permanently tied low. The SPI timeout will reset the interface if idle for 64 conversion cycles.

9.5.1.7 SPI Communication During Power-Down Mode

When the START pin is low or the device is in power-down mode, only the RDATA, RDATAC, SDATAC, WAKEUP, and NOP commands can be issued. The RDATA command can be used to repeatedly read the last conversion result during power-down mode. Other commands do not function because the internal clock is shut down to save power during power-down mode.

9.5.2 Data Format

The device provides 24 bits of data in binary twos complement format. The size of one code (LSB) is calculated using Equation 20.

Equation 20. 1 LSB = (2 × VREF / Gain) / 224 = +FS / 223

A positive full-scale (FS) input [VIN ≥ (+FS – 1 LSB) = (VREF / Gain – 1 LSB)] produces an output code of 7FFFFFh and a negative full-scale input (VIN ≤ –FS = –VREF / Gain) produces an output code of 800000h. The output clips at these codes for signals that exceed full-scale. Table 18 summarizes the ideal output codes for different input signals.

Table 18. Ideal Output Code vs Input Signal

INPUT SIGNAL, VIN
(AINP – AINN)
IDEAL OUTPUT CODE(1)
≥ FS (223 – 1) / 223 7FFFFFh
FS / 223 000001h
0 000000h
–FS / 223 FFFFFFh
≤ –FS 800000h
(1) Excludes effects of noise, linearity, offset, and gain errors.

Mapping of the analog input signal to the output codes is shown in Figure 77.

ADS1246 ADS1247 ADS1248 ai_code_transition_bas501.gif Figure 77. Code Transition Diagram

9.5.3 Commands

The device offers 13 commands to control device operation as shown in Table 19. Some of the commands are stand-alone commands (WAKEUP, SLEEP, SYNC, RESET, SYSOCAL, SYSGCAL, and SELFOCAL). There are three additional commands used to control the read of data from the device (RDATA, RDATAC, and SDATAC). The commands to read (RREG) and write (WREG) configuration register data from and to the device require additional information as part of the instruction. A no-operation command (NOP) can be used to clock out data from the device without clocking in a command.

Operands:

  • n = number of registers to be read or written (number of bytes – 1)
  • r = register (0 to 15)
  • x = don't care

Table 19. SPI Commands

COMMAND(1) DESCRIPTION 1st COMMAND BYTE 2nd COMMAND BYTE
WAKEUP Exit power-down mode 0000 000x (00h, 01h)
SLEEP Enter power-down mode 0000 001x (02h, 03h)
SYNC Synchronize ADC conversions 0000 010x (04h, 05h) 0000 010x (04,05h)
RESET Reset to default values 0000 011x (06h, 07h)
NOP No operation 1111 1111 (FFh)
RDATA Read data once 0001 001x (12h, 13h)
RDATAC Read data continuous mode 0001 010x (14h, 15h)
SDATAC Stop read data continuous mode 0001 011x (16h, 17h)
RREG Read from register rrrr 0010 rrrr (2xh) 0000 nnnn
WREG Write to register rrrr 0100 rrrr (4xh) 0000 nnnn
SYSOCAL System offset calibration 0110 0000 (60h)
SYSGCAL System gain calibration 0110 0001 (61h)
SELFOCAL Self offset calibration 0110 0010 (62h)
Restricted Restricted command.
Never send to the device.
1111 0001 (F1h)
(1) When the START pin is low or the device is in power-down mode, only the RDATA, RDATAC, SDATAC, WAKEUP, and NOP commands can be issued.

9.5.3.1 WAKEUP (0000 000x)

Use the WAKEUP command to power up the device after a SLEEP command. After execution of the WAKEUP command, the device powers up on the falling edge of the eighth SCLK.

9.5.3.2 SLEEP (0000 001x)

The SLEEP command places the device into power-down mode. When the SLEEP command is issued, the device completes the current conversion and then goes into power-down mode. Note that this command does not automatically power down the internal voltage reference; see the VREFCON bits in MUX1 for each device for further details.

To exit power-down mode, issue the WAKEUP command. Single conversions can be performed by issuing a WAKEUP command followed by a SLEEP command.

Both WAKEUP and SLEEP are the software command equivalents of using the START pin to control the device, as shown in Figure 78.

NOTE

If the START pin is held low, a WAKEUP command will not power up the device. When using the SLEEP command, CS must be held low for the duration of the power-down mode.

ADS1246 ADS1247 ADS1248 ai_spi_sleep_wakeup_sbas426.gif Figure 78. SLEEP and WAKEUP Commands Operation

9.5.3.3 SYNC (0000 010x)

The SYNC command resets the ADC digital filter and starts a new conversion. The DRDY pin from multiple devices connected to the same SPI bus can be synchronized by issuing a SYNC command to all of devices simultaneously.

ADS1246 ADS1247 ADS1248 ai_spi_sync_sbas426.gif Figure 79. SYNC Command Operation

9.5.3.4 RESET (0000 011X)

The RESET command restores the registers to the respective default values. This command also resets the digital filter. RESET is the command equivalent of using the RESET pin to reset the device. However, the RESET command does not reset the serial interface. If the RESET command is issued when the serial interface is out of synchonization due to a glitch on SCLK, the device does not reset. The CS pin can be used to reset the serial interface first, and then a RESET command can be issued to reset the device. The RESET command holds the registers and the decimation filter in a reset state for 0.6 ms when the system clock frequency is 4.096 MHz, similar to the hardware reset. Therefore, SPI communication can be only be started 0.6 ms after the RESET command is issued, as shown in Figure 80.

ADS1246 ADS1247 ADS1248 ai_spi_reset_sbas426.gif Figure 80. SPI Communication after an SPI Reset

9.5.3.5 RDATA (0001 001x)

The RDATA command loads the most recent conversion result into the output register. After issuing this command, the conversion result is read out by sending 24 SCLKs, as shown in Figure 81. This command also works in RDATAC mode.

ADS1246 ADS1247 ADS1248 ai_read_once_bas426.gif Figure 81. Read Data Once

When performing multiple reads of the conversion result, the RDATA command can be sent when the last eight bits of the conversion result are being shifted out during the course of the first read operation by taking advantage of the duplex communication nature of the serial interface, as shown in Figure 82.

ADS1246 ADS1247 ADS1248 ai_tim_rdata_bas426.gif Figure 82. Using RDATA in Full-Duplex Mode

9.5.3.6 RDATAC (0001 010x)

The RDATAC command enables read data continuous mode. This is the default mode after a power up or reset. In read data continuous mode, new conversion results are automatically loaded onto DOUT. The conversion result can be received from the device after the DRDY signal goes low by sending 24 SCLKs. It is not necessary to read back all the bits, as long as the number of bits read out is a multiple of eight. The RDATAC command must be issued after DRDY goes low, and the command takes effect on the next DRDY.

Be sure to complete data retrieval (conversion result or register read-back) before DRDY returns low, or the resulting data will be corrupt. Successful register read operations in RDATAC mode require the knowledge of when the next DRDY falling edge occurs.

ADS1246 ADS1247 ADS1248 ai_read_cont_bas426.gif Figure 83. Read Data Continuously

9.5.3.7 SDATAC (0001 011x)

The SDATAC command terminates read data continuous mode. In stop read data continuous mode, the conversion result is not automatically loaded onto DOUT when DRDY goes low, and register read operations can be performed without interruption from new conversion results being loaded into the output shift register. Use the RDATA command to retrieve conversion data. The SDATAC command takes effect after the next DRDY.

If DRDY is not actively monitored for data conversions, the stop read data continuous mode is the preferred method of reading data. In this mode, a read of ADC data is not interrupted by the completion of a new ADC conversion.

9.5.3.8 RREG (0010 rrrr, 0000 nnnn)

The RREG command outputs the data from up to 15 registers, starting with the register address specified as part of the instruction. The number of registers read is one plus the value of the second byte. If the count exceeds the remaining registers, the addresses wrap back to the beginning. The two byte command structure for RREG is listed below.

  • First Command Byte: 0010 rrrr, where rrrr is the address of the first register to read.
  • Second Command Byte: 0000 nnnn, where nnnn is the number of bytes to read –1.
  • Byte(s): data read from the registers are clocked out with NOPs.

It is not possible to use the full-duplex nature of the serial interface when reading out the register data. For example, a SYNC command cannot be issued when reading out the VBIAS and MUX1 data, as shown in Figure 84. Any command sent during the readout of the register data is ignored. Thus, TI recommends sending NOPs through DIN when reading out the register data.

ADS1246 ADS1247 ADS1248 ai_read_reg_bas426.gif Figure 84. Read from Register

9.5.3.9 WREG (0100 rrrr, 0000 nnnn)

The WREG command writes to the registers, starting with the register specified as part of the instruction. The number of registers that are written is one plus the value of the second byte. The command structure for WREG is listed below.

  • First Command Byte: 0100 rrrr, where rrrr is the address of the first register to be written.
  • Second Command Byte: 0000 nnnn, where nnnn is the number of bytes to be written – 1.
  • Byte(s): data to be written to the registers.

ADS1246 ADS1247 ADS1248 ai_spi_wreg_sbas426.gif Figure 85. Write to Register

9.5.3.10 SYSOCAL (0110 0000)

The SYSOCAL command initiates a system offset calibration. For a system offset calibration, the inputs must be externally shorted to a voltage within the input common mode range. The inputs should be near the mid-supply voltage of (AVDD + AVSS) / 2. The OFC register is updated when the command completes. Timing for the calibration commands can be found in Figure 86.

ADS1246 ADS1247 ADS1248 ai_calibration_command_sbas426.gif Figure 86. Calibration Command

9.5.3.11 SYSGCAL (0110 0001)

The SYSGCAL command initiates the system gain calibration. For a system gain calibration, the input should be set to full-scale. The FSC register is updated after this operation. Timing for the calibration commands can be found in Figure 86.

9.5.3.12 SELFOCAL (0110 0010)

The SELFOCAL command initiates a self offset calibration. The device internally shorts the inputs to mid-supply and performs the calibration. The OFC register is updated after this operation. Timing for the calibration commands can be found in Figure 86.

9.5.3.13 NOP (1111 1111)

This is a no-operation command. This is used to clock out data without clocking in a command.

9.5.3.14 Restricted Command (1111 0001)

This is a restricted command. This command should never be issued to the device.

9.6 Register Maps

9.6.1 ADS1246 Register Map

Table 20. ADS1246 Register Map

ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
00h BCS BCS[1:0] 0 0 0 0 0 1
01h VBIAS 0 0 0 0 0 0 VBIAS[1:0]
02h MUX1 CLKSTAT 0 0 0 0 MUXCAL[2:0]
03h SYS0 0 PGA[2:0] DR[3:0]
04h OFC0 OFC[7:0]
05h OFC1 OFC[15:8]
06h OFC2 OFC[23:16]
07h FSC0 FSC[7:0]
08h FSC1 FSC[15:8]
09h FSC2 FSC[23:16]
0Ah ID ID[3:0] DRDY MODE 0 0 0

9.6.2 ADS1246 Detailed Register Definitions

9.6.2.1 BCS—Burn-out Current Source Register (offset = 00h) [reset = 01h]

These bits control the sensor burn-out detect current source.

Figure 87. Burn-out Current Source Register
7 6 5 4 3 2 1 0
BCS[1:0] 0 0 0 0 0 1
R/W-0h R-0h R-0h R-0h R-0h R-0h R-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = variable

Table 21. Burn-out Current Source Register Field Descriptions

Bit Field Type Reset Description
7:6 BCS[1:0] R/W 0h Burn-out Detect Current Source
These bits control the setting of the sensor burn-out detect current source
00: Burn-out current source off (default)
01: Burn-out current source on, 0.5 μA
10: Burn-out current source on, 2 μA
11: Burn-out current source on, 10 μA
5:0 RESERVED R 01h Reserved
Always write 000001

9.6.2.2 VBIAS—Bias Voltage Register (offset = 01h) [reset = 00h]

This register enables a bias voltage on the analog inputs.

Figure 88. Bias Voltage Register
7 6 5 4 3 2 1 0
0 0 0 0 0 0 VBIAS[1:0]
R-0h R-0h R-0h R-0h R-0h R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = variable

Table 22. Bias Voltage Register Field Descriptions

Bit Field Type Reset Description
7:2 RESERVED R 00h Reserved
Always write 000000
1 VBIAS[1] R/W 0h VBIAS[1] Voltage Enable
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AINN
0: Bias voltage is not enabled (default)
1: Bias voltage is applied to AINN
0 VBIAS[0] R/W 0h VBIAS[0] Voltage Enable
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AINP
0: Bias voltage is not enabled (default)
1: Bias voltage is applied to AINP

9.6.2.3 MUX—Multiplexer Control Register (offset = 02h) [reset = x0h]

Figure 89. Multiplexer Control Register
7 6 5 4 3 2 1 0
CLKSTAT 0 0 0 0 MUXCAL[2:0]
R-xh R-0h R-0h R-0h R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = variable

Table 23. Multiplexer Control Register Field Descriptions

Bit Field Type Reset Description
7 CLKSTAT R xh Clock status
This bit is read-only and indicates whether the internal oscillator or external clock is being used.
0: Internal oscillator in use
1: External clock in use
6:3 RESERVED R 0h Reserved
Always write 0000
2:0 MUXCAL R/W 0h System Monitor Control
These bits are used to select a system monitor. The MUXCAL selection supercedes the selections from the VBIAS register.
000: Normal operation (default)
001: Offset calibration. The analog inputs are disconnected and AINP and AINN are internally connected to mid-supply (AVDD + AVSS) / 2.
010: Gain calibration. The analog inputs are connected to the voltage reference.
011: Temperature measurement. The inputs are connected to a diode circuit that produces a voltage proportional to the ambient temperature of the device.

Table 24 lists the ADC input connection and PGA settings for each MUXCAL setting. The PGA setting reverts to the original SYS0 register setting when MUXCAL is taken back to normal operation or offset measurement.

Table 24. MUXCAL Settings

MUXCAL[2:0] PGA GAIN SETTING ADC INPUT
000 Set by SYS0 register Normal operation
001 Set by SYS0 register Offset calibration: inputs shorted to mid-supply (AVDD + AVSS) / 2
010 Forced to 1 Gain calibration: V(REFP) – V(REFN) (full-scale)
011 Forced to 1 Temperature measurement diode

9.6.2.4 SYS0—System Control Register 0 (offset = 03h) [reset = 00h]

Figure 90. System Control Register 0
7 6 5 4 3 2 1 0
0 PGA[2:0] DR[3:0]
R-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = variable

Table 25. System Control Register 0 Field Descriptions

Bit Field Type Reset Description
7 RESERVED R 0h Reserved
This bit must always be set to 0
6:4 PGA[2:0] R/W 0h Gain Setting for PGA
These bits determine the gain of the PGA
000: PGA = 1 (default)
001: PGA = 2
010: PGA = 4
011: PGA = 8
100: PGA = 16
101: PGA = 32
110: PGA = 64
111: PGA = 128
3:0 DR[3:0] R/W 0h Data Output Rate Setting
These bits determine the data output rate of the ADC
0000: DR = 5 SPS (default)
0001: DR = 10 SPS
0010: DR = 20 SPS
0011: DR = 40 SPS
0100: DR = 80 SPS
0101: DR = 160 SPS
0110: DR = 320 SPS
0111: DR = 640 SPS
1000: DR = 1000 SPS
1001 to 1111: DR = 2000 SPS

9.6.2.5 OFC—Offset Calibration Coefficient Registers (offset = 04h, 05h, 06h) [reset = 00h, 00h, 00h]

These bits make up the offset calibration coefficient register of the ADS1246.

Figure 91. Offset Calibration Coefficient Registers
7 6 5 4 3 2 1 0
OFC[7:0]
R/W-00h
15 14 13 12 11 10 9 8
OFC[15:8]
R/W-00h
23 22 21 20 19 18 17 16
OFC[23:16]
R/W-00h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = variable

Table 26. Offset Calibration Coefficient Register Field Descriptions

Bit Field Type Reset Description
23:0 OFC[23:0] R/W 000000h Offset Calibration Register
Three registers compose the ADC 24-bit offset calibration word. The 24-bit word is twos complement format and is internally left-shifted to align with the ADC 24-bit conversion result. The ADC subtracts the register value from the conversion result before full scale operation.

9.6.2.6 FSC—Full-Scale Calibration Coefficient Registers (offset = 07h, 08h, 09h) [reset = PGA dependent]

These bits make up the full-scale calibration coefficient register. The reset value for FSC is factory-trimmed for each PGA setting. The factory-trimmed FSC reset value is automatically loaded whenever the PGA setting is changed.

Figure 92. Full-Scale Calibration Coefficient Registers
7 6 5 4 3 2 4 0
FSC[7:0]
R/W-xxh
15 14 13 12 11 10 9 8
FSC[15:8]
R/W-xxh
23 22 21 20 19 18 17 16
FSC[23:16]
R/W-xxh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = variable

Table 27. Full-Scale Calibration Coefficient Register Field Descriptions

Bit Field Type Reset Description
23:0 FSC[23:0] R/W xxxxxxh Full-Scale Calibration Register
Three registers compose the ADC 24-bit full-scale calibration word. The 24-bit word is straight binary. The ADC divides the register value by the FSC register by 400000h to derive the scale factor for calibration. After the offset calibration, the ADC multiplies the scale factor by the conversion result. The factory-trimmed FSC reset value is automatically loaded whenever the PGA setting is changed.

9.6.2.7 ID—ID Register (offset = 0Ah) [reset = x0h]

Figure 93. ID Register
7 6 5 4 3 2 1 0
ID[3:0] DRDY MODE 0 0 0
R-xh R/W-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = variable

Table 28. ID Register Field Descriptions

Bit Field Type Reset Description
7:4 ID[3:0] R xh Revision Identification
Read-only, factory-programmed bits; used for revision identification.
3 DRDY MODE R/W 0h Data Ready Mode Setting
This bit sets the DOUT/DRDY pin functionality. In either setting of the DRDY MODE bit, the dedicated DRDY pin continues to indicate data ready, active low.
0: DOUT/DRDY pin functions only as Data Out (default)
1: DOUT/DRDY pin functions both as Data Out and Data Ready, active low(1)
2:0 RESERVED R 0h RESERVED
These bits must always be set to 000
(1) Cannot be used in SDATAC mode

9.6.3 ADS1247 and ADS1248 Register Map

Table 29. ADS1247 and ADS1248 Register Map

ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
00h MUX0 BCS[1:0] MUX_SP[2:0] MUX_SN[2:0]
01h VBIAS VBIAS[7:0]
02h MUX1 CLKSTAT VREFCON[1:0] REFSELT[1:0] MUXCAL[2:0]
03h SYS0 0 PGA[2:0] DR[3:0]
04h OFC0 OFC[7:0]
05h OFC1 OFC[15:8]
06h OFC2 OFC[23:16]
07h FSC0 FSC[7:0]
08h FSC1 FSC[15:8]
09h FSC2 FSC[23:16]
0Ah IDAC0 ID[3:0] DRDY MODE IMAG[2:0]
0Bh IDAC1 I1DIR[3:0] I2DIR[3:0]
0Ch GPIOCFG IOCFG[7:0]
0Dh GPIODIR IODIR[7:0]
0Eh GPIODAT IODAT[7:0]

9.6.4 ADS1247 and ADS1248 Detailed Register Definitions

9.6.4.1 MUX0—Multiplexer Control Register 0 (offset = 00h) [reset = 01h]

This register allows any combination of differential inputs to be selected on any of the input channels. Note that this setting can be superceded by the MUXCAL and VBIAS bits.

Figure 94. Multiplexer Control Register 0
7 6 5 4 3 2 1 0
BCS[1:0] MUX_SP[2:0] MUX_SN[2:0]
R/W-0h R/W-0h R/W-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = variable

Table 30. Multiplexer Control Register 0 Register Field Descriptions

Bit Field Type Reset Description
7:6 BCS[1:0] R/W 0h Burn-out Detect Current Source Register
These bits control the setting of the sensor burnout detect current source
00: Burn-out current source off (default)
01: Burn-out current source on, 0.5 μA
10: Burn-out current source on, 2 μA
11: Burn-out current source on, 10 μA
5:3 MUX_SP[2:0] R/W 0h Multiplexer Selection - ADC Positive Input
Positive input channel selection bits
000: AIN0 (default)
001: AIN1
010: AIN2
011: AIN3
100: AIN4 (ADS1248 only)
101: AIN5 (ADS1248 only)
110: AIN6 (ADS1248 only)
111: AIN7 (ADS1248 only)
2:0 MUX_SN[2:0] R/W 1h Multiplexer Selection - ADC Negative Input
Negative input channel selection bits
000: AIN0
001: AIN1 (default)
010: AIN2
011: AIN3
100: AIN4 (ADS1248 only)
101: AIN5 (ADS1248 only)
110: AIN6 (ADS1248 only)
111: AIN7 (ADS1248 only)

9.6.4.2 VBIAS—Bias Voltage Register (offset = 01h) [reset = 00h]

Figure 95. Bias Voltage Register (ADS1247)
7 6 5 4 3 2 1 0
0 0 0 0 VBIAS[3:0]
R-0h R-0h R-0h R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = variable

Table 31. Bias Voltage Register Field Descriptions (ADS1247)

Bit Field Type Reset Description
7:4 RESERVED R 0h Reserved
Always write 0000
3 VBIAS[3] R/W 0h VBIAS[3] Voltage Enable
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN3
0: Bias voltage is not enabled (default)
1: Bias voltage is applied to AIN3
2 VBIAS[2] R/W 0h VBIAS[2] Voltage Enable
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN2
0: Bias voltage is not enabled (default)
1: Bias voltage is applied to AIN2
1 VBIAS[1] R/W 0h VBIAS[1] Voltage Enable
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN1
0: Bias voltage is not enabled (default)
1: Bias voltage is applied to AIN1
0 VBIAS[0] R/W 0h VBIAS[0] Voltage Enable
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN0
0: Bias voltage is not enabled (default)
1: Bias voltage is applied to AIN0
Figure 96. Bias Voltage Register (ADS1248)
7 6 5 4 3 2 1 0
VBIAS[7:0]
R/W-00h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = variable

Table 32. Bias Voltage Register Field Descriptions (ADS1248)

Bit Field Type Reset Description
7 VBIAS[7] R/W 0h VBIAS[7] Voltage Enable
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN7
0: Bias voltage is not enabled (default)
1: Bias voltage is applied to AIN7
6 VBIAS[6] R/W 0h VBIAS[6] Voltage Enable
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN6
0: Bias voltage is not enabled (default)
1: Bias voltage is applied to AIN6
5 VBIAS[5] R/W 0h VBIAS[5] Voltage Enable
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN5
0: Bias voltage is not enabled (default)
1: Bias voltage is applied to AIN5
4 VBIAS[4] R/W 0h VBIAS[4] Voltage Enable
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN4
0: Bias voltage is not enabled (default)
1: Bias voltage is applied to AIN4
3 VBIAS[3] R/W 0h VBIAS[3] Voltage Enable
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN3
0: Bias voltage is not enabled (default)
1: Bias voltage is applied to AIN3
2 VBIAS[2] R/W 0h VBIAS[2] Voltage Enable
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN2
0: Bias voltage is not enabled (default)
1: Bias voltage is applied to AIN2
1 VBIAS[1] R/W 0h VBIAS[1] Voltage Enable
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN1
0: Bias voltage is not enabled (default)
1: Bias voltage is applied to AIN1
0 VBIAS[0] R/W 0h VBIAS[0] Voltage Enable
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN0
0: Bias voltage is not enabled (default)
1: Bias voltage is applied to AIN0

9.6.4.3 MUX1—Multiplexer Control Register 1 (offset = 02h) [reset = x0h]

Figure 97. Multiplexer Control Register 1
7 6 5 4 3 2 1 0
CLKSTAT VREFCON[1:0] REFSELT[1:0] MUXCAL[2:0]
R-xh R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = variable

Table 33. Multiplexer Control Register 0 Register Field Descriptions

Bit Field Type Reset Description
7 CLKSTAT R xh Clock Status
This bit is read-only and indicates whether the internal oscillator or external clock is being used
0: Internal oscillator in use
1: External clock in use
6:5 VREFCON[1:0] R/W 0h Internal Reference Control
These bits control the internal voltage reference. These bits allow the reference to be turned on or off completely, or allow the reference state to follow the state of the device. Note that the internal reference is required for operation of the IDAC functions.
00: Internal reference is always off (default)
01: Internal reference is always on
10 or 11: Internal reference is on when a conversion is in progress and powers-down when the device receives a SLEEP command or the START pin is taken low
4:3 REFSELT[1:0] R/W 0h Reference Select Control
These bits select the reference input for the ADC.
00: REFP0 and REFN0 reference inputs selected (default)
01: REFP1 and REFN1 reference inputs selected (ADS1248 only)
10: Internal reference selected
11: Internal reference selected and internally connected to REFP0 and REFN0 input pins
2:0 MUXCAL[2:0](1) R/W 0h System Monitor Control
These bits are used to select a system monitor. The MUXCAL selection supercedes selections from the MUX0, MUX1, and VBIAS registers (includes MUX_SP, MUX_SN, VBIAS, and reference input selections).
000: Normal operation (default)
001: Offset calibration. The analog inputs are disconnected and AINP and AINN are internally connected to mid-supply (AVDD + AVSS) / 2.
010: Gain calibration. The analog inputs are connected to the voltage reference.
011: Temperature measurement. The inputs are connected to a diode circuit that produces a voltage proportional to the ambient temperature of the device.
100: REF1 monitor. The analog inputs are disconnected and AINP and AINN are internally connected to (V(REFP1) – V(REFN1)) / 4 (ADS1248 only)
101: REF0 monitor. The analog inputs are disconnected and AINP and AINN are internally connected to (V(REFP0) – V(REFN0)) / 4
110: Analog supply monitor. The analog inputs are disconnected and AINP and AINN are internally connected to (AVDD – AVSS) / 4
111: Digital supply monitor. The analog inputs are disconnected and AINP and AINN are internally connected to (DVDD – DGND) / 4
(1) When using either reference monitor, the internal reference should be enabled.

Table 34 provides the ADC input connection and PGA settings for each MUXCAL setting. The PGA setting reverts to the original SYS0 register setting when MUXCAL is taken back to normal operation or offset measurement.

Table 34. MUXCAL Settings

MUXCAL[2:0] PGA GAIN SETTING ADC INPUT
000 Set by SYS0 register Normal operation
001 Set by SYS0 register Inputs shorted to mid-supply (AVDD + AVSS) / 2
010 Forced to 1 V(REFP) – V(REFN) (full-scale)
011 Forced to 1 Temperature measurement diode
100 Forced to 1 (V(REFP1) – V(REFN1)) / 4
101 Forced to 1 (V(REFP0) – V(REFN0)) / 4
110 Forced to 1 (AVDD – AVSS) / 4
111 Forced to 1 (DVDD – DGND) / 4

9.6.4.4 SYS0—System Control Register 0 (offset = 03h) [reset = 00h]

Figure 98. System Control Register 0
7 6 5 4 3 2 1 0
0 PGA[2:0] DR[3:0]
R-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = variable

Table 35. System Control Register 0 Field Descriptions

Bit Field Type Reset Description
7 RESERVED R 0h Reserved
This bit must always be set to 0
6:4 PGA[2:0] R/W 0h Gain Setting for PGA
These bits determine the gain of the PGA
000: PGA = 1 (default)
001: PGA = 2
010: PGA = 4
011: PGA = 8
100: PGA = 16
101: PGA = 32
110: PGA = 64
111: PGA = 128
3:0 DR[3:0] R/W 0h Data Output Rate Setting
These bits determine the data output rate of the ADC
0000: DR = 5 SPS (default)
0001: DR = 10 SPS
0010: DR = 20 SPS
0011: DR = 40 SPS
0100: DR = 80 SPS
0101: DR = 160 SPS
0110: DR = 320 SPS
0111: DR = 640 SPS
1000: DR = 1000 SPS
1001 to 1111: DR = 2000 SPS

9.6.4.5 OFC—Offset Calibration Coefficient Register (offset = 04h, 05h, 06h) [reset = 00h, 00h, 00h]

These bits make up the offset calibration coefficient register of the ADS1247 and ADS1248.

Figure 99. Offset Calibration Coefficient Register
7 6 5 4 3 2 1 0
OFC[7:0]
R/W-00h
15 14 13 12 11 10 9 8
OFC[15:8]
R/W-00h
23 22 21 20 19 18 17 16
OFC[23:16]
R/W-00h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = variable

Table 36. Offset Calibration Coefficient Register Field Descriptions

Bit Field Type Reset Description
23:0 OFC[23:0] R/W 000000h Offset Calibration Register
Three registers compose the ADC 24-bit offset calibration word. The 24-bit word is twos complement format and is internally left-shifted to align with the ADC 24-bit conversion result. The ADC subtracts the register value from the conversion result before full scale operation.

9.6.4.6 FSC—Full-Scale Calibration Coefficient Register (offset = 07h, 08h, 09h) [reset = PGA dependent]

These bits make up the full-scale calibration coefficient register. The reset value for FSC is factory-trimmed for each PGA setting. The factory-trimmed FSC reset value is automatically loaded whenever the PGA setting is changed.

Figure 100. Full-Scale Calibration Coefficient Register
7 6 5 4 3 2 4 0
FSC[7:0]
R/W-xxh
15 14 13 12 11 10 9 8
FSC[15:8]
R/W-xxh
23 22 21 20 19 18 17 16
FSC[23:16]
R/W-xxh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = variable

Table 37. Full-Scale Calibration Coefficient Register Field Descriptions

Bit Field Type Reset Description
23:0 FSC[23:0] R/W xxxxxxh Full-Scale Calibration Register
Three registers compose the ADC 24-bit full-scale calibration word. The 24-bit word is straight binary. The ADC divides the register value by the FSC register by 400000h to derive the scale factor for calibration. After the offset calibration, the ADC multiplies the scale factor by the conversion result. The factory-trimmed FSC reset value is automatically loaded whenever the PGA setting is changed.

9.6.4.7 IDAC0—IDAC Control Register 0 (offset = 0Ah) [reset = x0h]

Figure 101. IDAC Control Register 0
7 6 5 4 3 2 1 0
ID[3:0] DRDY MODE IMAG[2:0]
R-xh R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = variable

Table 38. IDAC Control Register 0 Field Descriptions

Bit Field Type Reset Description
7:4 ID[3:0] R xh Revision Identification
Read-only, factory-programmed bits; used for revision identification.
3 DRDY MODE R/W 0h Data Ready Mode Setting
This bit sets the DOUT/DRDY pin functionality. In either setting of the DRDY MODE bit, the dedicated DRDY pin continues to indicate data ready, active low.
0: DOUT/DRDY pin functions only as Data Out (default)
1: DOUT/DRDY pin functions both as Data Out and Data Ready, active low(1)
2:0 IMAG[2:0] R/W 0h IDAC Excitation Current Magnitude
The ADS1247 and ADS1248 have two excitation current sources (IDACs) that can be used for sensor excitation. The IMAG bits control the magnitude of the excitation current. The IDACs require the internal reference to be on.
000: off (default)
001: 50 μA
010: 100 μA
011: 250 μA
100: 500 μA
101: 750 μA
110: 1000 μA
111: 1500 μA
(1) Cannot be used in SDATAC mode

9.6.4.8 IDAC1—IDAC Control Register 1 (offset = 0Bh) [reset = FFh]

Figure 102. IDAC Control Register 1 (ADS1247)
7 6 5 4 3 2 1 0
1 1 I1DIR[1:0] 1 1 I2DIR[1:0]
R-1h R-1h R/W-3h R-1h R-1h R/W-3h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = variable
Figure 103. IDAC Control Register 1 (ADS1248)
7 6 5 4 3 2 1 0
I1DIR[3:0] I2DIR[3:0]
R/W-Fh R/W-Fh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = variable

The two IDACs on the ADS1248 can be routed to either the IEXC1 and IEXC2 output pins or directly to the analog inputs.

Table 39. IDAC Control Register Field Descriptions

Bit Field Type Reset Description
7:4 I1DIR[3:0] R/W Fh IDAC Excitation Current Output 1
These bits select the output pin for the first excitation current source
0000: AIN0
0001: AIN1
0010: AIN2
0011: AIN3
0100: AIN4 (ADS1248 only)
0101: AIN5 (ADS1248 only)
0110: AIN6 (ADS1248 only)
0111: AIN7 (ADS1248 only)
10x0: IEXC1 (ADS1248 only)
10x1: IEXC2 (ADS1248 only)
11xx: Disconnected (default)
3:0 I2DIR[3:0] R/W Fh IDAC Excitation Current Output 2
These bits select the output pin for the second excitation current source
0000: AIN0
0001: AIN1
0010: AIN2
0011: AIN3
0100: AIN4 (ADS1248 only)
0101: AIN5 (ADS1248 only)
0110: AIN6 (ADS1248 only)
0111: AIN7 (ADS1248 only)
10x0: IEXC1 (ADS1248 only)
10x1: IEXC2 (ADS1248 only)
11xx: Disconnected (default)

9.6.4.9 GPIOCFG—GPIO Configuration Register (offset = 0Ch) [reset = 00h]

Figure 104. GPIO Configuration Register (ADS1247)
7 6 5 4 3 2 1 0
0 0 0 0 IOCFG[3:0]
R-0h R-0h R-0h R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = variable

Table 40. GPIO Configuration Register Field Descriptions (ADS1247)

Bit Field Type Reset Description
7:4 RESERVED R 0h Reserved
Always write 0000
3 IOCFG[3] R/W 0h GPIO[3] (AIN3) Pin Configuration
0: GPIO[3] is not enabled (default)
1: GPIO[3] is applied to AIN3
2 IOCFG[2] R/W 0h GPIO[2] (AIN2) Pin Configuration
0: GPIO[2] is not enabled (default)
1: GPIO[2] is applied to AIN2
1 IOCFG[1] R/W 0h GPIO[1] (REFN0) Pin Configuration
0: GPIO[1] is not enabled (default)
1: GPIO[1] is applied to REFN0
0 IOCFG[0] R/W 0h GPIO[0] (REFP0) Pin Configuration
0: GPIO[0] is not enabled (default)
1: GPIO[0] is applied to REFP0
Figure 105. GPIO Configuration Register (ADS1248)
7 6 5 4 3 2 1 0
IOCFG[7:0]
R/W-00h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = variable

Table 41. GPIO Configuration Register Field Descriptions (ADS1248)

Bit Field Type Reset Description
7 IOCFG[7] R/W 0h GPIO[7] (AIN7) Pin Configuration
0: GPIO[7] is not enabled (default)
1: GPIO[7] is applied to AIN7
6 IOCFG[6] R/W 0h GPIO[6] (AIN6) Pin Configuration
0: GPIO[6] is not enabled (default)
1: GPIO[6] is applied to AIN6
5 IOCFG[5] R/W 0h GPIO[5] (AIN5) Pin Configuration
0: GPIO[5] is not enabled (default)
1: GPIO[5] is applied to AIN5
4 IOCFG[4] R/W 0h GPIO[4] (AIN4) Pin Configuration
0: GPIO[4] is not enabled (default)
1: GPIO[4] is applied to AIN4
3 IOCFG[3] R/W 0h GPIO[3] (AIN3) Pin Configuration
0: GPIO[3] is not enabled (default)
1: GPIO[3] is applied to AIN3
2 IOCFG[2] R/W 0h GPIO[2] (AIN2) Pin Configuration
0: GPIO[2] is not enabled (default)
1: GPIO[2] is applied to AIN2
1 IOCFG[1] R/W 0h GPIO[1] (REFN0) Pin Configuration
0: GPIO[1] is not enabled (default)
1: GPIO[1] is applied to REFN0
0 IOCFG[0] R/W 0h GPIO[0] (REFP0) Pin Configuration
0: GPIO[0] is not enabled (default)
1: GPIO[0] is applied to REFP0

9.6.4.10 GPIODIR—GPIO Direction Register (offset = 0Dh) [reset = 00h]

Figure 106. GPIO Direction Register (ADS1247)
7 6 5 4 3 2 1 0
0 0 0 0 IODIR[3:0]
R-0h R-0h R-0h R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = variable

Table 42. GPIO Direction Register Field Descriptions (ADS1247)

Bit Field Type Reset Description
7:4 RESERVED R 0h Reserved
Always write 0000
3 IODIR[3] R/W 0h GPIO[3] (AIN3) Pin Direction
Configures GPIO[3] as a GPIO input or GPIO output
0: GPIO[3] is an output (default)
1: GPIO[3] is an input
2 IODIR[2] R/W 0h GPIO[2] (AIN2) Pin Direction
Configures GPIO[2] as a GPIO input or GPIO output
0: GPIO[2] is an output (default)
1: GPIO[2] is an input
1 IODIR[1] R/W 0h GPIO[1] (REFN0) Pin Direction
Configures GPIO[1] as a GPIO input or GPIO output
0: GPIO[1] is an output (default)
1: GPIO[1] is an input
0 IODIR[0] R/W 0h GPIO[0] (REFP0) Pin Direction
Configures GPIO[0] as a GPIO input or GPIO output
0: GPIO[0] is an output (default)
1: GPIO[0] is an input
Figure 107. GPIO Direction Register (ADS1248)
7 6 5 4 3 2 1 0
IODIR[7:0]
R/W-00h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = variable

Table 43. GPIO Direction Register Field Descriptions (ADS1248)

Bit Field Type Reset Description
7 IODIR[7] R/W 0h GPIO[7] (AIN7) Pin Direction
Configures GPIO[7] as a GPIO input or GPIO output
0: GPIO[7] is an output (default)
1: GPIO[7] is an input
6 IODIR[6] R/W 0h GPIO[6] (AIN6) Pin Direction
Configures GPIO[6] as a GPIO input or GPIO output
0: GPIO[6] is an output (default)
1: GPIO[6] is an input
5 IODIR[5] R/W 0h GPIO[5] (AIN5) Pin Direction
Configures GPIO[5] as a GPIO input or GPIO output
0: GPIO[5] is an output (default)
1: GPIO[5] is an input
4 IODIR[4] R/W 0h GPIO[4] (AIN4) Pin Direction
Configures GPIO[4] as a GPIO input or GPIO output
0: GPIO[4] is an output (default)
1: GPIO[4] is an input
3 IODIR[3] R/W 0h GPIO[3] (AIN3) Pin Direction
Configures GPIO[3] as a GPIO input or GPIO output
0: GPIO[3] is an output (default)
1: GPIO[3] is an input
2 IODIR[2] R/W 0h GPIO[2] (AIN2) Pin Direction
Configures GPIO[2] as a GPIO input or GPIO output
0: GPIO[2] is an output (default)
1: GPIO[2] is an input
1 IODIR[1] R/W 0h GPIO[1] (REFN0) Pin Direction
Configures GPIO[1] as a GPIO input or GPIO output
0: GPIO[1] is an output (default)
1: GPIO[1] is an input
0 IODIR[0] R/W 0h GPIO[0] (REFP0) Pin Direction
Configures GPIO[0] as a GPIO input or GPIO output
0: GPIO[0] is an output (default)
1: GPIO[0] is an input

9.6.4.11 GPIODAT—GPIO Data Register (offset = 0Eh) [reset = 00h]

Figure 108. GPIO Data Register (ADS1247)
7 6 5 4 3 2 1 0
0 0 0 0 IODAT[3:0]
R-0h R-0h R-0h R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = variable

Table 44. GPIO Data Register Field Descriptions (ADS1247)

Bit Field Type Reset Description
7:4 RESERVED R 0h Reserved
Always write 0000
3 IODAT[3] R/W 0h GPIO[3] (AIN3) Pin Data
Configured as an output, read returns the register value
Configured as an input, write sets the register value only
0: GPIO[3] is low (default)
1: GPIO[3] is high
2 IODAT[2] R/W 0h GPIO[2] (AIN2) Pin Data
Configured as an output, read returns the register value
Configured as an input, write sets the register value only
0: GPIO[2] is low (default)
1: GPIO[2] is high
1 IODAT[1] R/W 0h GPIO[1] (REFN0) Pin Data
Configured as an output, read returns the register value
Configured as an input, write sets the register value only
0: GPIO[1] is low (default)
1: GPIO[1] is high
0 IODAT[0] R/W 0h GPIO[0] (REFP0) Pin Data
Configured as an output, read returns the register value
Configured as an input, write sets the register value only
0: GPIO[0] is low (default)
1: GPIO[0] is high
Figure 109. GPIO Data Register (ADS1248)
7 6 5 4 3 2 1 0
IODAT[7:0]
R/W-00h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = variable

Table 45. GPIO Data Register Field Descriptions (ADS1248)

Bit Field Type Reset Description
7 IODAT[7] R/W 0h GPIO[7] (AIN7) Pin Data
Configured as an output, read returns the register value
Configured as an input, write sets the register value only
0: GPIO[7] is low (default)
1: GPIO[7] is high
6 IODAT[6] R/W 0h GPIO[6] (AIN6) Pin Data
Configured as an output, read returns the register value
Configured as an input, write sets the register value only
0: GPIO[6] is low (default)
1: GPIO[6] is high
5 IODAT[5] R/W 0h GPIO[5] (AIN5) Pin Data
Configured as an output, read returns the register value
Configured as an input, write sets the register value only
0: GPIO[5] is low (default)
1: GPIO[5] is high
4 IODAT[4] R/W 0h GPIO[4] (AIN4) Pin Data
Configured as an output, read returns the register value
Configured as an input, write sets the register value only
0: GPIO[4] is low (default)
1: GPIO[4] is high
3 IODAT[3] R/W 0h GPIO[3] (AIN3) Pin Data
Configured as an output, read returns the register value
Configured as an input, write sets the register value only
0: GPIO[3] is low (default)
1: GPIO[3] is high
2 IODAT[2] R/W 0h GPIO[2] (AIN2) Pin Data
Configured as an output, read returns the register value
Configured as an input, write sets the register value only
0: GPIO[2] is low (default)
1: GPIO[2] is high
1 IODAT[1] R/W 0h GPIO[1] (REFN0) Pin Data
Configured as an output, read returns the register value
Configured as an input, write sets the register value only
0: GPIO[1] is low (default)
1: GPIO[1] is high
0 IODAT[0] R/W 0h GPIO[0] (REFP0) Pin Data
Configured as an output, read returns the register value
Configured as an input, write sets the register value only
0: GPIO[0] is low (default)
1: GPIO[0] is high