SCBS809G December   2005  – September 2017 UCC2895-EP

PRODUCTION DATA.  

  1. 1Features
  2. 2Description
  3. 3Revision History
  4. 4Pin Configuration and Functions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  6. 6Application and Implementation
    1. 6.1 Programming DELAB, DELCD, and Adaptive Delay Set (ADS)
    2. 6.2 Circuit Description
  7. 7Device and Documentation Support
    1. 7.1 Receiving Notification of Documentation Updates
    2. 7.2 Community Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

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4 Pin Configuration and Functions

DW Package
20-Pin SOIC
Top View
UCC2895-EP po3_cbs809.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
ADS 11 I

Adaptive delay set. This function sets the ratio between the maximum and minimum programmed output delay dead time. When ADS is connected directly to CS, no delay modulation occurs. Maximum delay modulation occurs when ADS is grounded. In this case, delay time is four times longer when CS = 0 than when CS = 2 V (the peak current threshold). ADS changes the output voltage on the delay (DELAB and DELCD) pins by:

UCC2895-EP equation3a_cbs809.gif

where VCS and VADS are in volts. ADS must be limited to between 0 V and 2.5 V and must be less than, or equal to, CS. DELAB and DELCD also are clamped to a minimum of 0.5 V.
CS 12 I Current sense. CS is the inverting input of the current-sense comparator, and the noninverting input of the overcurrent comparator and the ADS amplifier. The CS signal is used for cycle-by-cycle current limiting in peak current-mode control and for overcurrent protection in all cases with a secondary threshold for output shutdown. An output disable initiated by an overcurrent fault also results in a restart cycle, called soft stop, with full soft start.
CT 7 I

Oscillator timing capacitor (see Figure 9). The UCC2895-EP oscillator charges CT via a programmed current. The waveform on CT is a sawtooth, with a peak voltage of 2.35 V. The approximate oscillator period is calculated by:

UCC2895-EP equation4a_cbs809.gif

where CT is in farads, RT is in ohms, and tOSC is in seconds. CT can range from 100 pF to 880 pF. Note that a large CT and a small RT combination results in extended fall times on the CT waveform. The increased fall time increases the SYNC pulse width, thus, limiting the maximum phase shift between OUTA/ OUTB and OUTC/ OUTD outputs, which limits the maximum duty cycle of the converter.
DELAB, DELCD 9, 10 I

Delay programming between complementary outputs. DELAB programs the dead time between switching of OUTA and OUTB, and DELCD programs the dead time between OUTC and OUTD. This delay is introduced between complementary outputs in the same leg of the external bridge. The UCC2895-EP allows the user to select the delay in which the resonant switching of the external power stages takes place. Separate delays are provided for the two half bridges to accommodate differences in resonant capacitor charging currents. The delay in each stage is set according to the formula:

UCC2895-EP equation5a_cbs809.gif

where VDEL is in volts, RDEL is in ohms, and tDELAY is in seconds. DELAB and DELCD can source
approximately 1-mA maximum. Delay resistors must be chosen so that this maximum is not exceeded. Programmable output delay can be defeated by tying DELAB and/or DELCD to REF. For optimum performance, keep stray capacitance on these pins at < 10 pF.
EAN 1 I Error amplifier negative. Inverting input to the error amplifier. Keep below 3.6 V for proper operation.
EAOUT 2 I/O Error amplifier output. EAOUT also is connected internally to the noninverting input of the PWM comparator and the no-load comparator. EAOUT is internally clamped to the soft-start voltage. The no-load comparator shuts down the output stages when EAOUT falls below 500 mV and allows the outputs to turn on again when EAOUT rises above 600 mV.
EAP 20 I Error amplifier positive. Noninverting input to the error amplifier. Keep below 3.6 V for proper operation.
GND 5 — Ground. Chip ground for all circuits except the output stages.
OUTA,
OUTB,
OUTC,
OUTD		 18, 17, 14, 13 O Outputs. These outputs are 100-mA complementary MOS drivers and are optimized to drive FET driver circuits. OUTA and OUTB are fully complementary (assuming no programmed delay). They operate near 50% duty cycle and one-half the oscillating frequency. OUTA and OUTB are intended to drive one half-bridge circuit in an external power stage. OUTC and OUTD drive the other half bridge and have the same characteristics as OUTA and OUTB. OUTC is phase shifted with respect to OUTA, and OUTD is phase shifted with respect to OUTB. Note that changing the phase relationship of OUTC and OUTD, with respect to OUTA and OUTB, requires other than the nominal 50% duty ratio on OUTC and OUTD during those transients.
PGND 16 — Output stage ground. To keep output switching noise from critical analog circuits, the UCC2895-EP has two different ground connections. PGND is the ground connection for the high-current output stages. Both GND and PGND must be electrically tied together closely near the IC. Also, since PGND carries high current, board traces must be low impedance.
RAMP 3 I Inverting input of PWM comparator. RAMP receives either the CT waveform in voltage and average current-mode controls, or the current signal (plus slope compensation) in peak current-mode control. An internal discharge transistor is provided on RAMP, which is triggered during the oscillator dead time.
REF 4 O 5-V ± 1.2% voltage reference. REF supplies power to internal circuitry, and also can supply up to 5 mA to external loads. The reference is shut down during undervoltage lockout, but is operational during all other disable modes. For best performance, bypass with a 0.1-μF low ESR, low ESL capacitor to ground. Do not use more than 1 μF.
RT 8 I

Oscillator timing resistor (see Figure 9). The oscillator in the UCC2895-EP operates by charging an external timing capacitor, CT, with a fixed current programmed by RT. RT current is calculated as:

UCC2895-EP equation6a_cbs809.gif

RT can range from 40 kΩ to 120 kΩ. Soft-start charging and discharging current also are programmed by IRT.
SS/DISB 19 I

Soft start/disable. SS/DISB combines two independent functions:

  • Disable mode. A rapid shutdown of the chip is accomplished by any one of the following: externally forcing SS/DISB below 0.5 V, externally forcing REF below 4 V, VDD dropping below the UVLO threshold, or an overcurrent fault is sensed (CS = 2.5 V).
    In the case of REF pulled below 4 V or an UVLO condition, SS/DISB actively is pulled to ground via an internal MOSFET switch. If an overcurrent is sensed, SS/DISB sinks a current of 10 × IRT until SS/DISB falls below 0.5 V.
    Note that, if SS/DISB is externally forced below 0.5 V, the pin starts to source current equal to IRT. Also note that the only time the part switches into the low IDD current mode is when the part is in undervoltage lockout.
  • Soft-start mode. After a fault or disable condition has passed and VDD is above the start threshold and/or SS/DISB falls below 0.5 V during a soft stop, SS/DISB switches to a soft-start mode. The pin now sources current equal to IRT. A user-selected capacitor on SS/DISB determines the soft start and soft-start time. In addition, a resistor in parallel with the capacitor may be used, limiting the maximum voltage on SS/DISB. Note that SS/DISB actively clamps the EAOUT voltage to approximately the SS/DISB voltage during both soft-start, soft-stop, and disable conditions.
SYNC 6 I/O Synchronization (see Figure 9). SYNC is bidirectional. When used as an output, SYNC can be used as a clock, which is the same as the chip’s internal clock. When used as an input, SYNC overrides the chip’s internal oscillator and acts as its clock signal. This bidirectional feature allows synchronization of multiple power supplies. SYNC also internally discharges the CT capacitor and any filter capacitors that are present on RAMP. The internal SYNC circuitry is level sensitive, with an input low threshold of 1.9 V and an input high threshold of 2.1 V. A resistor as small as 3.9 kΩ may be tied between SYNC and GND to reduce the synchronization pulse width.
VDD 15 I Power supply. VDD must be bypassed with a minimum of a 1-μF low ESR, low ESL capacitor to ground.