10.1 Layout Guidelines

• High frequency bypass Capacitor C7 should be placed arcoss Pin 2 and 5 as close as you can get it to the pins.
• Resistor R15 and C7 form a low pass filter and the connection of R15 and C7 should be as close to the VDD pin as possible.
• C9 should be put as close to CS pin and R10 as possible. This forms a low pass filter with R10.
• The connection for C9 and R10 should be as close to the CS pin as possible.
• C9 may not be required in all designs. However, it is wise to put a place holder for it in your design.
• The VS pin controls the output voltage through the transformer turns ratio and the voltage divider of R7 and R9. The trace with between the R7, R9 and VS pin should be as short as possible to reduce and eliminate possible EMI coupling.
• The IC ground and power ground should meet at the return of the bulk capacitors (C4 and C5). Ensure that high frequency and high current from the power stage does not go through the signal ground
  • The high frequency and high current path that you need to be cautious of on the primary is C4, C5 +, T1(P1,P2), Q1e, Q1c, R13 to the return of C4 and C5.
• Keep all high current loops as short as possible.
• Keep all high current and high frequency traces away from or perpendicular to other traces in the design.
• Traces on the voltage clamp formed by D1, R1, D4 and C4 as short as possible.
• C4 return needs to be as close to the bulk capacitor supply as possible. This reduces the magnitude of dv/dt caused by large di/dt.
• Avoid mounting semiconductors under magnetics.

10.2 Layout Example

Figure 28. PCB Layout Example

Figure 29. 5-W USB Adapter Schematic