Table 2. Design Parameters

8.2.2.1 Output Current Calculation

The first step is to determine the maximum load current on the output.

Equation 36.

8.2.2.2 Bridge Rectifier

The maximum RMS input-line current is given by Equation 37:

Equation 37.

The peak input current is given by Equation 38:

Equation 38.

The maximum average rectified line current is given by Equation 39:

Equation 39.

A typical bridge rectifier has a forward voltage drop V_F of 0.95 V. The power loss in the rectifier bridge can be calculated by Equation 40:

Equation 40.

The bridge rectifier must be rated to carry the full line current. The voltage rating of the bridge should be at least 600 V. The bridge rectifier also carries the full inrush current as the bulk capacitor C_OUT charges when line is connected.

8.2.2.3 PFC Inductor (L₁ and L₂)

The selection of the PFC inductor value may be based on a number of different considerations. Cost, core size, EMI filter, and inductor ripple current are some of the factors that have an influence. For this design we choose the inductor so that at the minimum input voltage the peak to peak ripple (ΔI_L) has the same amplitude as the peak of line current in each phase. The line current flows equally in the two phases so ΔI_I is half I_{in_pk} calculated in Equation 38. The inductor is calculated by Equation 41.

Equation 41.

where

• V_OUT is the PFC stage output voltage
• f_SW is the switching frequency
• ΔI_L is the allowed peak-to-peak ripple current.

D is the PFC stage duty cycle at 120 V_IN (peak of 85 Vrms line) and is given by Equation 42:

Equation 42.

The peak current in each boost inductor is then:

Equation 43.

The inductor specifications are:

• Inductance: 160 µH
• Current: 4 A

8.2.2.4 PFC MOSFETs (M₁ and M₂)

The main specifications for the PFC MOSFETs are:

• B_VDSS, drain source breakdown voltage: ≥650 V
• R_DS(on), ON-state drain source resistance: 520 mΩ at 25°C, estimate 1 Ω at 125°C
• C_DSS, output capacitance: 32 pF
• tr, devise rise time: 12 ns
• tf, device fall time: 16 ns

The losses in the device are calculated by Equation 44 and Equation 45. These calculations are approximations because the losses are dependent on parameters which are not well controlled. For example, the R_DS(on) of a MOSFET can vary by a factor of 2 from 25°C to 125°C. Therefore several iterations may be needed to choose an optimum device for an application different than the one discussed.

Each phase carries half the load power so the conduction losses are estimated by:

Equation 44.

The switching losses in each MOSFET are estimated by:

Equation 45.

The total losses in each MOSFET are then:

Equation 46.

8.2.2.5 PFC Diode

Reverse recovery losses can be significant in a CCM boost converter. A Silicon Carbide Diode is chosen here because it has no reverse recovery charge (Q_RR) and therefore zero reverse recovery losses.

Equation 47.

8.2.2.6 PFC Output Capacitor

The value of the output capacitor is governed by the required hold-up time and the allowable ripple on the output.

The hold-up time depends on the load current and the minimum acceptable voltage at the output.

The value of the output capacitor must be large enough to provide the required hold-up time and keep the ripple voltage at twice line frequency within acceptable limits. Normally a capacitance value of about 0.6 μF per Watt of output power is a reasonable compromise where hold-up time is not significant. At 300 W this would indicate a capacitance of about 200 μF.

The low frequency (at twice line frequency) rms voltage ripple on V_OUT is given by Equation 48:

Equation 48.

The resulting low frequency current in the capacitor is:

Equation 49.

8.2.2.7 Current Loop Feedback Configuration
(Sizing of the Current Transformer Turns Ratio and Sense Resistor (R_S)

A current-sense transformer (CT) is typically used in high-power applications to sense inductor current in order to avoid the losses inherent in the use of a current sensing resistor. For average current-mode control, the entire inductor current waveform is required; however low-frequency CTs are obviously impracticable. Normally, two high-frequency CTs are used, one in the switching leg to obtain the up-slope current and one in the diode leg to obtain the down-slope current. These two current signals are summed together to form the entire inductor current, but this is not necessary with the UCC28070.

A major advantage of the UCC28070 design is the current synthesis function, which internally recreates the inductor current down-slope during the switching period OFF-time. This eliminates the need for the diode-leg CT in each phase, significantly reducing space, cost and complexity. A single resistor programs the synthesizer down slope, as previously discussed in the Current Synthesizer section.

A number of trade-offs must be made in the selection of the CT. Various internal and external factors influence the size, cost, performance, and distortion contribution of the CT.

These factors include, but are not limited to:

• Turns-ratio (N_CT)
• Magnetizing inductance (L_M)
• Leakage inductance (L_LK)
• Volt-microsecond product (Vμs)
• Distributed capacitance (C_d)
• Series resistance (R_SER)
• External diode drop (V_D)
• External current sense resistor (R_S)
• External reset network

Traditionally, the turns-ratio and the current sense resistor are selected first. Some iterations may be needed to refine the selection once the other considerations are included.

In general, 50 ≤ N_CT ≤ 200 is a reasonable range from which to choose. If N_CT is too low, there may be high power loss in R_S and insufficient L_M. If too high, there could be excessive L_LK and C_d. (A one-turn primary winding is assumed.)

Figure 25. Current Sense Transformer Equivalent Circuit

A major contributor to distortion of the input current is the effect of magnetizing current on the CT output signal (i_RS). A higher turns-ratio results in a higher L_M for a given core size. L_M should be high enough that the magnetizing current (i_M) generated is a very small percentage of the total transformed current. This is an impossible criterion to maintain over the entire current range, because i_M unavoidably becomes a larger fraction of i_RS as the input current decreases toward zero. The effect of i_M is to steal some of the signal current away from R_S, reducing the CSx voltage and effectively understating the actual current being sensed. At low currents, this understatement can be significant and CAOx increases the current-loop duty-cycle in an attempt to correct the CSx input(s) to match the IMO reference voltage. This unwanted correction results in overstated current on the input wave shape in the regions where the CT understatement is significant, such as near the AC line zero crossings. It can affect the entire waveform to some degree under the high line, light-load conditions.

The sense resistor R_S is chosen, in conjunction with N_CT, to establish the sense voltage at CSx to be about 3 V at the center of the reflected inductor ripple current under maximum load. The goal is to maximize the average signal within the common-mode input range V_CMCAO of the CAOx current-error amplifiers, while leaving room for the peaks of the ripple current within V_CMCAO. The design condition should be at the lowest maximum input power limit as determined in the section on the Linear Multiplier and Quantized Voltage Feed Forward. If the inductor ripple current is so high as to cause V_CSx to exceed V_CMCAO, then R_S or N_CT or both must be adjusted to reduce peak V_CSx, which could reduce the average sense voltage center below 3 V. There is nothing wrong with this situation; but be aware that the signal is more compressed between full- and no-load, with potentially more distortion at light loads.

The matter of volt-second balancing is important, especially with the widely varying duty-cycles in the PFC stage. Ideally, the CT is reset once each switching period; that is, the OFF-time Vμs product equals the ON-time Vμs product. On-time Vμs is the time-integral of the voltage across L_M generated by the series elements R_SER, L_LK, D, and R_S. Off-time Vμs is the time-integral of the voltage across the reset network during the OFF-time. With passive reset, Vμs-off is unlikely to exceed Vμs-on. Sustained unbalance in the on or off Vμs products leads to core saturation and a total loss of the current-sense signal. Loss of V_CSx causes V_CAOx to quickly rise to its maximum, programming a maximum duty-cycle at any line condition. This, in turn causes the boost inductor current to increase without control, until the system fuse or some component failure interrupts the input current.

It is vital that the CT has plenty of Vμs design-margin to accommodate various special situations where there may be several consecutive maximum duty-cycle periods at maximum input current, such as during peak current limiting.

Maximum Vμs(on) can be estimated by:

Equation 50.

where

• all factors are maximized to account for worst-case transient conditions
• t_ON(max) occurs during the lowest dither frequency, if frequency dithering is enabled

For design margin, a CT rating of approximately 5 × Vμs(on)max or higher is suggested. The contribution of V_RS varies directly with the line current. However, V_D may have a significant voltage even at near-zero current, so substantial Vμs(on) may accrue at the zero-crossings where the duty-cycle is maximum. V_RSER is the least contributor, and often can be neglected if R_SER < R_S. V_LK is developed by the di/dt of the sensed current, and is not observable externally. However, its impact is considerable, given the sub-microsecond rise-time of the current signal plus the slope of the inductor current. Fortunately, most of the built-up Vμs across L_M during the ON-time is removed during the fall-time at the end of the duty-cycle, leaving a lower net Vμs(on) to be reset during the OFF-time. Nevertheless, the CT must, at the very minimum, be capable of sustaining the full internal Vμs(on)max built up until the moment of turn-off within a switching period.

Vμs(off) may be generated with a resistor or Zener diode, using the i_M as bias current.

Figure 26. Possible Reset Networks

To accommodate various CT circuit designs and prevent the potentially destructive result due to CT saturation, the UCC28070’s maximum duty-cycle must be programmed such that the resulting minimum OFF-time accomplishes the required worst-case reset. (See the PWM Frequency and Duty-Cycle Clamp section of the data sheet for more information on sizing R_DMX) Be aware that excessive C_d in the CT can interfere with effective resetting, because the maximum reset voltage is not reached until after 1/4-period of the CT self-resonant frequency. A higher turns-ratio results in higher C_d [3], so a trade-off between N_CTand D_MAX must be made.

The selected turns-ratio also affects L_M and L_LK, which vary proportionally to the square of the turns. Higher L_M is good, while higher L_LK is not. If the voltage across L_M during the ON-time is assumed to be constant (which it is not, but close enough to simplify) then the magnetizing current is an increasing ramp.

This upward ramping current subtracts from i_RS, which affects V_CSx especially heavily at the zero-crossings and light loads, as stated earlier. With a reduced peak at V_CSx, the current synthesizer starts the down-slope at a lower voltage, further reducing the average signal to CAOx and further increasing the distortion under these conditions. If low input current distortion at very light loads is required, special mitigation methods may need to be developed to accomplish that goal.

8.2.2.8 Current Sense Offset and PWM Ramp for Improved Noise Immunity

To improve noise immunity at extremely light loads, TI recommends adding a PWM ramp with a DC offset to the current sense signals. Electrical components R_TA, R_TB, R_OA, R_OB, C_TA, C_TB, D_PA1, D_PA2, D_PB1, D_PB1 C_TA, and C_TB form a PWM ramp that is activated and deactivated by the gate drive outputs of the UCC28070. Resistor R_OA and R_OB add a DC offset to the CS resistors (R_SA and R_SB).

Figure 27. PWM Ramp and Offset Circuit

When the inductor current becomes discontinuous the boost inductors ring with the parasitic capacitances in the boost stages. This inductor current rings through the CTs causing a false current sense signal. Please refer to the following graphical representation of what the current sense signal looks like when the inductor current goes discontinuous.

Figure 28. False Current Sense Signal

To counter for the offset (V_OFF) just requires adjusting resistors R_OA and R_OB to ensure that when the unit goes discontinuous the current sense resistor is not seeing a positive current when it should be zero. Setting the offset to 120 mV is a good starting point and may need to be adjusted based on individual design criteria.

Equation 51.

Equation 52.

A small PWM ramp that is equal to 10% of the maximum current sense signal (V_S) less the offset can then be added by properly selecting R_TA, R_TB, C_TA and C_TB.

Equation 53.

Equation 54.