SLUSEX2A September   2025  – September 2025 UCC27734 , UCC27735

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Dynamic Electrical Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stages and Interlock
      2. 6.3.2 Enable Function (UCC277x5 Only)
      3. 6.3.3 Undervoltage Lockout (UVLO)
      4. 6.3.4 Level Shifter
      5. 6.3.5 Output Stage
      6. 6.3.6 Low Propagation Delays and Tightly Matched Outputs
      7. 6.3.7 HS Node dV/dt
      8. 6.3.8 Split Grounds (COM and VSS)
      9. 6.3.9 Operation Under Negative HS Voltage Condition
    4. 6.4 Device Functional Modes
      1. 6.4.1 Input and Output Logic Table
      2. 6.4.2 Operation Under 100% Duty Cycle Condition
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Selecting HI and LI Low Pass Filter Components (RHI, RLI, CHI, CLI)
        2. 7.2.2.2 Selecting Bootstrap Capacitor (CBOOT)
        3. 7.2.2.3 Selecting VDD Bypass Capacitor (CVDD)
        4. 7.2.2.4 Selecting Bootstrap Resistor (RBOOT)
        5. 7.2.2.5 Selecting Gate Resistor RHO/RLO
        6. 7.2.2.6 Selecting Bootstrap Diode
        7. 7.2.2.7 Estimate the UCC2773x Power Losses
        8. 7.2.2.8 Application Example Schematic Note
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
      2. 8.1.2 Development Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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5.5 Electrical Characteristics

At VDD=VHB=15V, COM=VHS=0, all voltages are with respect to COM, no load on LO and HO, –40°C < TJ < +150°C (unless otherwise noted). Currents are positive into and negative out of the specified terminal.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY BLOCK
VVDD ON Turn-on threshold voltage of VDD 8V UVLO 8.3 9.0 9.7 V
VVDD OFF Turn-off threshold voltage of VDD 8V UVLO 7.8 8.5 9.2
VVDD HYS Hysteresis of VDD 8V UVLO 0.6
VVHB ON Turn-on threshold voltage of VHB-VHS 8V UVLO 7.6 8.3 9.0
VVHB OFF Turn-off threshold voltage of VHB-VHS 8V UVLO 7.1 7.8 8.5
VVHB HYS Hysteresis of VHB-VHS 8V UVLO 0.5
IQDD Total quiescent VDD to VSS and COM supply current HI=LI=0 V or 5 V, DC on/off state 150 300 µA
IQCOM Quiescent VDD-COM supply current (UCC27735 only) HI=LI=0 V or 5 V, DC on/off state 55 100 µA
IQVSS Quiescent VDD-VSS supply current (UCC27735 only) HI=LI=0 V or 5 V, DC on/off state 110 300 µA
IQBS Quiescent HB-HS supply current HI=0 V or 5 V, HO in DC on/off state 85 180 µA
IBL Bootstrap supply leakage current (HB to COM + HB to VSS) HB=HS=700 V, VDD=COM=0 V 0.1 25 µA
INPUT AND ENABLE BLOCK
VINH , VENH Input Pin (HI, LI) and enable pin (EN) high threshold 1.7 2.1 2.5 V
VINL, VENL Input Pin (HI, LI) and enable pin (EN) low threshold 0.7 1.0 1.3 V
VINHYS, VENHYS Input Pin (HI, LI) and enable pin (EN) threshold hysteresis 1.1 V
IINL HI, LI input low bias current HI, LI = 0 V -5 5 µA
IINH HI, LI input high bias current HI, LI = 5 V 20 55 µA
IENL EN input low bias current (UCC27735 only) EN = 0 V -75 µA
IENH EN input high bias current (UCC27735 only) EN = 5 V -50 µA
RHI Pull down resistor on HI input pin HI, LI = 5 V 100 200 KΩ
RLI Pull down resistor on LI input pin HI, LI = 5 V 100 200 KΩ
REN Pull up resistor on EN pin (UCC27735 only) EN = 0 V 200 KΩ
OUTPUT BLOCK
VDD-VLOH LO output high voltage LI = 5V, ILO=-20mA 225 500 mV
VHB-VHOH HO output high voltage HI = 5V, IHO=-20mA 225 500 mV
VLOL LO output low voltage LI = 0V, ILO=20mA 20 40 mV
VHOL HO output low voltage HI = 0V, IHO=20mA 20 40 mV
RLOL, RHOL LO, HO output pull-down resistance ILO=IHO=20mA 1 2 Ω
RLOH, RHOH LO, HO output pull-up resistance ILO=IHO=-20mA 12.6 25
IGPK-(1) HO, LO output sink current HI=LI=0V, HO=LO=15V, PW<10us 4 A
IGPK+(1) HO, LO output source current HI=LI=5V, HO=LO=0V, PW<10us 3.5
(1) Ensured by design, not tested in production