ZHCSM73 September   2021 TUSB217A-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Timing Requirements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 High-speed Boost
      2. 8.3.2 RX Sensitivity
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low-speed (LS) Mode
      2. 8.4.2 Full-speed (FS) Mode
      3. 8.4.3 High-speed (HS) Mode
      4. 8.4.4 High-speed Downstream Port Electrical Compliance Test Mode
      5. 8.4.5 Shutdown Mode
      6. 8.4.6 I2C Mode
      7. 8.4.7 BC 1.2 Battery Charging Controller
    5. 8.5 TUSB217A-Q1 Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Test Procedure to Construct USB High-speed Eye Diagram
          1. 9.2.2.1.1 For a Host Side Application
          2. 9.2.2.1.2 For a Device Side Application
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 接收文档更新通知
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 静电放电警告
    5. 12.5 术语表

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机械数据 (封装 | 引脚)
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订购信息

8.3.1 High-speed Boost

The high-speed booster (combination of edge boost and DC boost) improves the eye width for USB2.0 high-speed signals. It is direction independent and by that is compatible to OTG systems. The BOOST pin is configuring the booster strength with different values of pull down resistors to set 4 levels of boosts, alternatively the boost level can be set via I2C register according to Section 8.4.6. Internal circuitry of the signal conditioner reduces possible overshoot.