ZHCS133B March   2011  – June 2015 TUSB1211

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用范围
    3. 1.3 说明
    4. 1.4 功能框图
  2. 2修订历史
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Diagram
      1. 3.1.1 Pin Attributes
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Power Consumption Summary
    5. 4.5  Electrical Characteristics - Analog Output Pins
    6. 4.6  Electrical Characteristics - Analog Input Pins
    7. 4.7  Digital I/O Electrical Characteristics - Non-ULPI Pins
    8. 4.8  Digital I/O Electrical Characteristics - Non-ULPI Pins
    9. 4.9  Electrical Characteristics - REFCLK
    10. 4.10 Electrical Characteristics - CLOCK Input
    11. 4.11 Electrical Characteristics - REFCLK
    12. 4.12 Electrical Characteristics - CK32K Clock Generator
    13. 4.13 Thermal Characteristics
    14. 4.14 REG3V3 Internal LDO Regulator Characteristics
    15. 4.15 REG1V8 Internal LDO Regulator Characteristics
    16. 4.16 REG1V5 Internal LDO Regulator Characteristics
    17. 4.17 Timers and Debounce
    18. 4.18 OTG VBUS Electrical
    19. 4.19 LS/FS Single-Ended Receivers
    20. 4.20 LS/FS Differential Receiver
    21. 4.21 LS Transmitter
    22. 4.22 FS Transmitter
    23. 4.23 HS Transmitter
    24. 4.24 Pullup and Pulldown Resistors
    25. 4.25 Autoresume Watchdog Timer
    26. 4.26 UART Transceiver
    27. 4.27 OTG ID Electrical
    28. 4.28 Electrical Specs - Charger Detection Currents
    29. 4.29 Electrical Specs - Resistance
    30. 4.30 Electrical Specs - Capacitance
    31. 4.31 Charger Detection Debounce and Wait Timing
    32. 4.32 ULPI Interface
      1. 4.32.1 ULPI Interface Timing
    33. 4.33 Power-On Timing Diagrams
      1. 4.33.1 Standard Power-up Timing
      2. 4.33.2 Hardware Charger Detection Power-Up Timing
    34. 4.34 Clock System
      1. 4.34.1 USB PLL Reference Clock
        1. 4.34.1.1 ULPI Input Clock Configuration
        2. 4.34.1.2 ULPI Output Clock Configuration
    35. 4.35 Clock System
      1. 4.35.1 Internal Clock Generator (32 kHz)
    36. 4.36 Power Management
      1. 4.36.1 Power Provider
    37. 4.37 Power Provider
      1. 4.37.1 REG3V3 Regulator
      2. 4.37.2 REG1V8 Regulator
      3. 4.37.3 REG1V5 Regulator
    38. 4.38 Power Control
  5. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1  USB On-The-Go (OTG) Feature
      2. 5.3.2  VBUS Detection Status Bits vs VBUS Comparators
      3. 5.3.3  USB Transceiver (PHY)
        1. 5.3.3.1 PHY Overview
      4. 5.3.4  LS/FS Single-Ended Receivers
      5. 5.3.5  LS/FS Differential Receiver
      6. 5.3.6  LS/FS Transmitter
      7. 5.3.7  HS Differential Receiver
      8. 5.3.8  HS Differential Transmitter
      9. 5.3.9  Autoresume
      10. 5.3.10 UART Transceiver
      11. 5.3.11 USB On-The-Go (OTG)
        1. 5.3.11.1 ID Detection Status Bits vs ID Comparators
      12. 5.3.12 USB Battery Charger Detection and ACA
      13. 5.3.13 USB Battery Charger Detection Modes
      14. 5.3.14 Accessory Charger Adapter (ACA) Detection
    4. 5.4 Register Maps
      1. 5.4.1  VENDOR_ID_LO
      2. 5.4.2  VENDOR_ID_HI
      3. 5.4.3  PRODUCT_ID_LO
      4. 5.4.4  PRODUCT_ID_HI
      5. 5.4.5  FUNC_CTRL
      6. 5.4.6  FUNC_CTRL_SET
      7. 5.4.7  FUNC_CTRL_CLR
      8. 5.4.8  IFC_CTRL
      9. 5.4.9  IFC_CTRL_SET
      10. 5.4.10 IFC_CTRL_CLR
      11. 5.4.11 OTG_CTRL
      12. 5.4.12 OTG_CTRL_SET
      13. 5.4.13 OTG_CTRL_CLR
      14. 5.4.14 USB_INT_EN_RISE
      15. 5.4.15 USB_INT_EN_RISE_SET
      16. 5.4.16 USB_INT_EN_RISE_CLR
      17. 5.4.17 USB_INT_EN_FALL
      18. 5.4.18 USB_INT_EN_FALL_SET
      19. 5.4.19 USB_INT_EN_FALL_CLR
      20. 5.4.20 USB_INT_STS
      21. 5.4.21 USB_INT_LATCH
      22. 5.4.22 DEBUG
      23. 5.4.23 SCRATCH_REG
      24. 5.4.24 SCRATCH_REG_SET
      25. 5.4.25 SCRATCH_REG_CLR
      26. 5.4.26 POWER_CONTROL
      27. 5.4.27 POWER_CONTROL_SET
      28. 5.4.28 POWER_CONTROL_CLR
      29. 5.4.29 VENDOR_SPECIFIC1
      30. 5.4.30 VENDOR_SPECIFIC1_SET
      31. 5.4.31 VENDOR_SPECIFIC1_CLR
      32. 5.4.32 VENDOR_SPECIFIC2_STS
      33. 5.4.33 VENDOR_SPECIFIC2_LATCH
      34. 5.4.34 VENDOR_SPECIFIC3
      35. 5.4.35 VENDOR_SPECIFIC3_SET
      36. 5.4.36 VENDOR_SPECIFIC3_CLR
      37. 5.4.37 VENDOR_SPECIFIC4
      38. 5.4.38 VENDOR_SPECIFIC4_SET
      39. 5.4.39 VENDOR_SPECIFIC4_CLR
      40. 5.4.40 VENDOR_SPECIFIC5
      41. 5.4.41 VENDOR_SPECIFIC5_SET
      42. 5.4.42 VENDOR_SPECIFIC5_CLR
      43. 5.4.43 VENDOR_SPECIFIC6
      44. 5.4.44 VENDOR_SPECIFIC6_SET
      45. 5.4.45 VENDOR_SPECIFIC6_CLR
  6. 6Application, Implementation, and Layout
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 Unused Pins Connection
      3. 6.2.3 Application Curves
    3. 6.3 Layout
      1. 6.3.1 Layout Guidelines
        1. 6.3.1.1 Ground
      2. 6.3.2 Layout Example
    4. 6.4 Power Supply Recommendations
  7. 7器件和文档支持
    1. 7.1 文档支持
      1. 7.1.1 相关文档　
      2. 7.1.2 Community Resources
    2. 7.2 商标
    3. 7.3 静电放电警告
    4. 7.4 Glossary
  8. 8机械、封装和可订购信息
    1. 8.1 封装信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

2 修订历史

Changes from A Revision (January 2012) to B Revision

  • Deleted 部分 特性 （根据提交的资源）Go
  • 已根据最新的 TI 标准布局更改文档Go
  • Changed pin F5 from A to D in the A/D column Go
  • Added the Analog Output Pins sectionGo
  • Added the word Non to the tile Non-ULPI Pins and replaced the Digital I/O Electrical Characteristics – Non-ULPI Pins table dataGo
  • Added the Timers and Debounce sectionGo
  • Added the OTG VBUS SpecificationsGo
  • Added the Pullup and Pulldown Resistors tableGo
  • Added Section 4.26 Go
  • Added the OTG ID Electrical tableGo
  • Added the ULPI Interface sectionGo
  • Added the Power-On Timing Diagrams sectionGo
  • Added the Internal Clock Generator (32 kHz)Go
  • Added the Power Provider section Go
  • Changed the location of paragraphs from Description to Detailed Description, subsection OverviewGo
  • Added the LS/FS Single-Ended Receivers sectionGo
  • Added the LS/FS Differential Receiver sectionGo
  • Added the LS/FS TransmitterGo
  • Added the HS Differential Receiver sectionGo
  • Added the HS Differential Transmitter sectionGo
  • Added the Autoresume sectionGo
  • Added the Register Map section Go
  • Added the Application and Implementation sectionGo
  • Deleted two List Items from the Unused Pins Connection sectionGo
  • Added the Layout sectionGo
  • Added the Power Supply Recommendations sectionGo