ZHCSFC8E August 2016 – January 2023 TUSB1046-DCI
PRODUCTION DATA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | SWAP_HPDIN | EQ_OVERRIDE | HPDIN_OVRRIDE | FLIPSEL | CTLSEL[1:0]. | ||
R | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | Reserved. | R | 00 | Reserved. |
5 | SWAP_HPDIN | R/W | 0 | 0 – HPDIN is in default location (Default) 1 – HPDIN location is swapped (PIN 23 to PIN 32, or PIN 32 to PIN23). |
4 | EQ_OVERRIDE | R/W | 0 | Setting of this field will allow software to use EQ settings from registers instead of value sample from pins. 0 – EQ settings based on sampled state of the EQ pins (SSEQ[1:0], EQ[1:0], and DPEQ[1:0]). 1 – EQ settings based on programmed value of each of the EQ registers |
3 | HPDIN_OVRRIDE | R/W | 0 | 0 – HPD IN based on state of HPD_IN pin (Default) 1 – HPD_IN high. |
2 | FLIPSEL | R/W | 0 | FLIPSEL. Refer to Table 7-5 and Table 7-6 for this field functionality. |
1:0 | CTLSEL[1:0]. | R/W | 01 | 00 – Disabled. All RX and TX for USB3 and DisplayPort are disabled. 01 – USB3.1 only enabled. (Default) 10 – Four DisplayPort lanes enabled. 11 – Two DisplayPort lanes and one USB3.1 |