ZHCSDL6C November   2014  – March 2019 TS3DDR4000

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      应用图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Static Electrical Characteristics
    6. 6.6 Dynamic Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Non-Volatile Dual In-line Memory Module (NVDIMM) application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 Load Isolation Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 接收文档更新通知
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 Static Electrical Characteristics

Unless otherwise noted the specification applies over the VDD range and operation junction temp of –40°C ≤ TJ ≤ 85°C. Typical values are for VDD = 3.3 V and TJ = 25°C.
PARAMETER TEST CONDITION MIN TYP MAX UNIT
RON On-state resistance Port A to B VDD = 2.375 V, VI/O = 1.2 V,
II/O = 10 mA		 – 8.3 11.2 Ω
Port A to C – 8.3 11.2 Ω
RON (FLAT) On-state resistance flatness for all I/Os Port A to B VDD = 2.375 V, VI/O = 1.2 V, II/O = 10 mA – 0.6 – Ω
Port A to C – 0.6 – Ω
∆RON On-state resistance match between channels Port A to B VDD = 2.375 V, VI/O = 1.2 V, II/O = 10 mA – 0.2 1.0 Ω
Port A to C – 0.2 1.0 Ω
IIH Control input high leakage current EN VDD = 3.6 V, V/EN = 1.4 V – – ±1 µA
VDD = 2.375 V, V/EN = 3.3 V – – ±1 µA
SEL1 VDD = 3.6 V, VSEL1 = 1.4 V – – ±1 µA
VDD = 2.375 V, VSEL1 = 3.3 V – – ±1 µA
SEL2 VDD = 3.6 V, VSEL2 = 1.4 V – – ±1 µA
VDD = 2.375 V, VSEL2 = 3.3 V – – ±1 µA
IIL Control input low leakage current EN VDD = 3.6 V, V/EN = 0 V – – ±0.5 µA
SEL1 VDD = 3.6 V, VSEL1 = 0 V – – ±0.5 µA
SEL2 VDD = 3.6 V, VSEL2 = 0 V – – ±0.5 µA
IOFF Leakage under power off condition for all I/Os EN VDD = 0 V, V/EN = 0 V, VI/O = 0 V to 3.3 V – – ±5 µA
VDD = 0 V, V//EN = 3.6 V, VI/O = 0 V to 3.3 V – – ±5 µA
SEL1 VDD = 0 V, VSEL1 = 0 V, VI/O = 0 V to 3.3 V – – ±5 µA
VDD = 0 V, VSEL1 = 3.6 V, VI/O = 0 V to 3.3 V – – ±5 µA
SEL2 VDD = 0 V, VSEL2 = 0 V, VI/O = 0 V to 3.3 V – – ±5 µA
VDD = 0 V, VSEL2 = 3.6 V, VI/O = 0 V to 3.3 V – – ±5 µA
IDD VDD supply current VDD = 3.6 V, II/O = 0 A, /EN = 0 V, VSEL1 = VSEL2= 0 V – 28 35 µA
VDD = 3.6 V, II/O = 0 A, /EN = 0 V, VSEL1 = VSEL2= 1.8 V – 40 48 µA
VDD = 3.6 V, II/O = 0 A, /EN = 0 V, VSEL1 = 0 V, VSEL2= 1.8 V – 40 44 µA
VDD = 3.6 V,II/O = 0 A, /EN = 0 V, VSEL1 = 1.8 V, VSEL2= 0 V – 40 44 µA
IDD, PD VDD supply current in power-down mode VDD = 3.6 V, II/O = 0 A, /EN = 1.8 V – 2 5 µA