SLOU186G August   2006  – May 2017 TRF7960 , TRF7961

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Typical Application
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Electrical Characteristics
    5. 5.5 Thermal Resistance Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Power Supplies
      1. 6.2.1 Negative Supply Connections
      2. 6.2.2 Digital I/O Interface
      3. 6.2.3 Supply Regulator Configuration
      4. 6.2.4 Power Modes
      5. 6.2.5 Timing Diagrams
    3. 6.3 Receiver - Analog Section
      1. 6.3.1 Received Signal Strength Indicator (RSSI)
      2. 6.3.2 Receiver - Digital Section
      3. 6.3.3 Transmitter
        1. 6.3.3.1 Transmitter - Analog Section
        2. 6.3.3.2 Transmitter - Digital Section
      4. 6.3.4 Direct Mode
      5. 6.3.5 Register Preset
    4. 6.4 Register Descriptions
      1. 6.4.1 Control Registers - Main Configuration Registers
      2. 6.4.2 Control Registers - Sublevel Configuration Registers
      3. 6.4.3 Status Registers
      4. 6.4.4 FIFO Control Registers
    5. 6.5 Direct Commands From MCU to Reader
      1. 6.5.1  Command Codes
      2. 6.5.2  Reset FIFO
      3. 6.5.3  Transmission With CRC
      4. 6.5.4  Transmission Without CRC
      5. 6.5.5  Delayed Transmission With CRC
      6. 6.5.6  Delayed Transmission Without CRC
      7. 6.5.7  Transmit Next Time Slot
      8. 6.5.8  Receiver Gain Adjust
      9. 6.5.9  Test External RF (RSSI at RX Input With TX Off)
      10. 6.5.10 Test Internal RF (RSSI at RX Input With TX On)
      11. 6.5.11 Block Receiver
      12. 6.5.12 Enable Receiver
    6. 6.6 Reader Communication Interface
      1. 6.6.1 Introduction
    7. 6.7 Parallel Interface Communication
      1. 6.7.1 Receive
      2. 6.7.2 Transmit
    8. 6.8 Serial Interface Communication
      1. 6.8.1 SPI Without SS* (Slave Select) Pin
      2. 6.8.2 SPI With SS* (Slave Select) Pin
        1. 6.8.2.1 FIFO Operation
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Schematics
  8. 8Device and Documentation Support
    1. 8.1  Getting Started and Next Steps
    2. 8.2  Device Nomenclature
    3. 8.3  Tools and Software
    4. 8.4  Documentation Support
    5. 8.5  Related Links
    6. 8.6  Community Resources
    7. 8.7  Trademarks
    8. 8.8  Electrostatic Discharge Caution
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

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Detailed Description

Overview

Figure 6-1 shows a typical application diagram for the TRF796x devices. A parallel or serial interface can be implemented for communication between the MCU and reader. Transmit and receive functions use internal encoders and decoders with a 12-byte FIFO register. For direct transmit or receive functions, the encoders and decoders can be bypassed so the MCU can process the data in real time. The transmitter has selectable output power levels of 100 mW (20 dBm) or 200 mW (23 dBm) into a 50-Ω load (5-V supply) and supports ASK or OOK modulation. Integrated voltage regulators ensure power-supply noise rejection for the complete reader system.

TRF7960 TRF7961 trf796xparallelb.gif Figure 6-1 Typical Application Diagram

Data transmission supports low-level encoding for ISO/IEC 15693, modified Miller for ISO/IEC 14443 A, high-bit-rate systems for ISO/IEC 14443, and Tag-it coding systems. Included with the data encoding is automatic generation of SOF, EOF, CRC, and parity bits.

The receiver system enables AM and PM demodulation using a dual-input architecture. The receiver also includes an automatic gain control option and selectable gain. Also included is a selectable bandwidth to cover a broad range of input subcarrier signal options. The received signal strength for AM and PM modulation is accessible through the RSSI register. The receiver output is a digitized subcarrier signal among a selectable protocol and bit rate as outlined in Table 6-13. A selected decoder delivers bit stream and a data clock as outputs.

The receiver system also includes a framing system. This system performs a CRC or parity check, removes the EOF and SOF settings, and organizes the data in bytes. Framed data is then accessible to the MCU through a 12-byte FIFO register and MCU interface. The framing supports ISO/IEC 14443 and ISO/IEC 15693 protocols.

The TRF796x supports data communication levels from 1.8 V to 5.5 V for the MCU I/O interface, while also providing a data synchronization clock. An auxiliary 20-mA regulator (pin 32) is available for additional system circuits.

Power Supplies

The positive supply pin, VIN (pin 2), has an input voltage range of 2.7 V to 5.5 V. The positive supply input sources three internal regulators with output voltages VDD_RF, VDD_A, and VDD_X that use external bypass capacitors for supply noise filtering. These regulators provide enhanced PSRR for the RFID reader system. Table 6-1 describes the power supplies.

The regulators are not independent and have common control bits for output voltage setting. The regulators can be configured to operate in either automatic or manual mode. The automatic regulator mode setting ensures an optimal compromise between regulator PSRR and highest possible supply voltage for RF output power. The manual mode allows the application to manually configure the regulator settings.

Table 6-1 Power Supplies

SUPPLY DESCRIPTION
VDD_RF The regulator VDD_RF (pin 3) is used to source the RF output stage. The voltage regulator can be set for either 5-V or 3-V operation.

When configured for 5-V operation, the output voltage can be set from 4.3 V to 5 V in 100-mV steps. The current sourcing capability for 5-V operation is 150 mA maximum over the adjusted output voltage range.

When configured for 3-V operation, the output voltage can be set from 2.7 V to 3.4 V, also in 100-mV steps. The current sourcing capability for 3-V operation is 100 mA maximum over the adjusted output voltage range.

VDD_A Regulator VDD_A (pin 1) supplies voltage to analog circuits within the reader chip. The voltage setting is divided in two ranges. When configured for 5-V operation, the output voltage is fixed at 3.5 V. When configured for 3-V operation, the output voltage can be set from 2.7 V to 3.4 V in 100-mV steps.

NOTE: The VDD_A and VDD_X regulators are configured together (their settings are not independent).

VDD_X Regulator VDD_X (pin 32) can be used to source the digital I/O of the reader chip together with other external system components. When configured for 5-V operation, the output voltage is fixed at 3.4 V. When configured for 3-V operation, the output voltage can be set from 2.7 to 3.4 V in 100-mV steps.

The total current sourcing capability of the VDD_X regulator is 20 mA (maximum) over the adjusted output range.

NOTE: The VDD_A and VDD_X regulators are configured together (their settings are not independent).

VDD_PA The VDD_PA pin (pin 4) is the positive supply pin for the RF output stage and is externally connected to the regulator output VDD_RF (pin 3).

Negative Supply Connections

The negative supply connections are all externally connected together (to GND). The substrate connection is VSS (pin 10), the analog negative supply is VSS_A (pin 15), the logic negative supply is VSS_D (pin 29), the RF output stage negative supply is VSS_TX (pin 6), and the negative supply for the RF receiver input is VSS_RX (pin 7).

Digital I/O Interface

To allow compatible I/O signal levels, the TRF796x has a separate supply input VDD_I/O (pin 16), with an input voltage range of 1.8 V to 5.5 V. This pin supplies the I/O interface (I/O_0 to I/O_7), IRQ, SYS_CLK, and DATA_CLK pins of the reader. In typical applications, VDD_I/O is connected directly to VDD_X to ensure that the I/O signal levels of the MCU are the same as the internal logic levels of the reader.

Supply Regulator Configuration

The supply regulators can be automatically or manually configured by the control bits. Table 6-2 lists the manual regulator settings for a 5-V system. Table 6-3 lists the manual regulator settings for a 3-V system. Table 6-4 and Table 6-5 list the automatic mode gain settings for 5-V and 3-V systems, respectively.

The automatic mode is the default configuration. In automatic mode, the regulators are automatically set every time the system is activated by asserting the EN input high. The internal regulators are also automatically reconfigured every time the automatic regulator selection bit is set high (on the rising edge).

The application can reset the automatic mode setting from a state in which the automatic setting bit is already high by changing the automatic setting bit from high to low to high. The regulator-configuration algorithm adjusts the regulator outputs 250 mV below the VIN level, but not higher than 5 V for VDD_RF, 3.5 V for VDD_A, and 3.4 V for VDD_X. This algorithm ensures the highest possible supply voltage for the RF output stage while maintaining an adequate PSRR (power supply rejection ratio). As an example, the application can improve the PSRR if there is a noisy supply voltage from VDD_X by increasing the target voltage difference across the VDD_X regulator as listed for automatic regulator settings in Table 6-4 and Table 6-5.

Table 6-2 Supply-Regulator Setting – Manual – 5-V System

BYTE ADDRESS OPTION BITS SETTING IN CONTROL REGISTER ACTION
B7 B6 B5 B4 B3 B2 B1 B0
0x00 1 5-V system
0x0B 0 Manual regulator setting
0x0B 0 1 1 1 VDD_RF = 5 V, VDD_A = 3.5 V, VDD_X = 3.4 V
0x0B 0 1 1 0 VDD_RF = 4.9 V, VDD_A = 3.5 V, VDD_X = 3.4 V
0x0B 0 1 0 1 VDD_RF = 4.8 V, VDD_A = 3.5 V, VDD_X = 3.4 V
0x0B 0 1 0 0 VDD_RF = 4.7 V, VDD_A = 3.5 V, VDD_X = 3.4 V
0x0B 0 0 1 1 VDD_RF = 4.6 V, VDD_A = 3.5 V, VDD_X = 3.4 V
0x0B 0 0 1 0 VDD_RF = 4.5 V, VDD_A = 3.5 V, VDD_X = 3.4 V
0x0B 0 0 0 1 VDD_RF = 4.4 V, VDD_A = 3.5 V, VDD_X = 3.4 V
0x0B 0 0 0 0 VDD_RF = 4.3 V, VDD_A = 3.5 V, VDD_X = 3.4 V

Table 6-3 Supply-Regulator Setting – Manual – 3-V System

BYTE ADDRESS OPTION BITS SETTING IN CONTROL REGISTER ACTION
B7 B6 B5 B4 B3 B2 B1 B0
0x00 0 3-V system
0x0B 0 Manual regulator setting
0x0B 0 1 1 1 VDD_RF = 3.4 V, VDD_A, VDD_X = 3.4 V
0x0B 0 1 1 0 VDD_RF = 3.3 V, VDD_A, VDD_X = 3.3 V
0x0B 0 1 0 1 VDD_RF = 3.2 V, VDD_A, VDD_X = 3.2 V
0x0B 0 1 0 0 VDD_RF = 3.1 V, VDD_A, VDD_X = 3.1 V
0x0B 0 0 1 1 VDD_RF = 3.0 V, VDD_A, VDD_X = 3.0 V
0x0B 0 0 1 0 VDD_RF = 2.9 V, VDD_A, VDD_X = 2.9 V
0x0B 0 0 0 1 VDD_RF = 2.8 V, VDD_A, VDD_X = 2.8 V
0x0B 0 0 0 0 VDD_RF = 2.7 V, VDD_A, VDD_X = 2.7 V

Table 6-4 Supply-Regulator Setting – Automatic – 5-V System

BYTE ADDRESS OPTION BITS SETTING IN CONTROL REGISTER ACTION
B7 B6 B5 B4 B3 B2(1) B1 B0
0x00 1 5-V system
0x0B 1 x 1 1 Automatic regulator setting; approximately 250-mV difference
0x0B 1 x 1 0 Automatic regulator setting; approximately 350-mV difference
0x0B 1 x 0 0 Automatic regulator setting; approximately 400-mV difference
x = Don't care

Table 6-5 Supply-Regulator Setting – Automatic – 3-V System

BYTE ADDRESS OPTION BITS SETTING IN CONTROL REGISTER ACTION
B7 B6 B5 B4 B3 B2(1) B1 B0
0x00 0 3-V system
0x0B 1 x 1 1 Automatic regulator setting; approximately 250-mV difference
0x0B 1 x 1 0 Automatic regulator setting; approximately 350-mV difference
0x0B 1 x 0 0 Automatic regulator setting; approximately 400-mV difference
x = Don't care

Power Modes

The chip has seven power states, which are controlled by two input pins (EN and EN2) and three bits in the Chip Status Control register (00h).

The main reader enable input is EN (which has a threshold level of 1 V [minimum]). Any input signal level from 1.8 V to VIN can be used. When EN is set high, all of the reader regulators are enabled, together with the 13.56-MHz oscillator, and the SYS_CLK output clock for an external MCU.

The auxiliary enable input EN2 has two functions:

  • A direct connection from EN2 to VIN ensures availability of the regulated supply (VDD_X) and an auxiliary clock signal (60 kHz) on the SYS_CLK output (same for the case EN = 0). This mode is intended for systems in which the MCU controlling the reader is also being supplied by the reader supply regulator (VDD_X) and the MCU clock is supplied by the SYS_CLK output of the reader. This lets the MCU supply and clock be available during power down.
  • EN2 enables start-up of the reader system from complete power down (EN = 0, EN2 = 0). In this case, the EN input is controlled by the MCU or other system device that is without supply voltage during complete power down (thus unable to control the EN input). A rising edge applied to the EN2 input (which has a 1-V threshold level) starts the reader supply system and 13.56-MHz oscillator (identical to condition EN = 1). This start-up mode lasts until all of the regulators have settled and the 13.56-MHz oscillator has stabilized. If the EN input is set high by the MCU (or other system device), the reader stays active. If the EN input is not set high within 100 µs after the SYS_CLK output is switched from auxiliary clock (60 kHz) to high-frequency clock (derived from the crystal oscillator), the reader system returns to a complete power-down mode. This option can be used to wake the reader system from complete power down by using a push-button switch or by sending a single pulse.

After the reader EN line is high, the other power modes are selected by control bits. Table 6-6 lists the power mode options and functions.

Table 6-6 Power Modes

BYTE ADDRESS OPTION BITS SETTING IN CHIP STATUS CONTROL REGISTER EN EN2 FUNCTIONALITY CURRENT
B7
stby
B6 B5
rfon
B4 B3
rf_pwr
B2 B1
rec_on
B0
0x00 0 0 Complete power down <1 µA
0x00 0 1 VDD_X available,
SYS_CLK auxiliary frequency 60 kHz is ON
120 µA
0x00 1 x x x 1 x All supply regulators active and in low power mode,
13.56-MHz oscillator on,
SYS_CLK clock available
1.5 mA
0x00 0 0 x 0 1 x All supply regulators active,
13.56-MHz oscillator on,
SYS_CLK clock available
3.5 mA
0x00 0 0 x 1 1 x All supply regulators active,
13.56-MHz oscillator on,
SYS_CLK clock available,
Receiver active
10 mA
0x00 0 1 1 x 1 x All supply regulators active,
13.56-MHz oscillator on,
SYS_CLK clock available,
Receiver active,
Transmitter active in half-power mode
70 mA
(at 5 V)
0x00 0 1 0 x 1 x All supply regulators active,
13.56-MHz oscillator running,
SYS_CLK clock available,
Receiver active,
Transmitter active in full-power mode
120 mA
(at 5 V)

During reader inactivity, the TRF796x can be placed in power-down mode (EN = 0). The power down can be complete (EN = 0, EN2 = 0) with no function running, or partial (EN = 0, EN2 = 1) with the regulated supply (VDD_X) and 60-kHz auxiliary clock (SYS_CLK) available to the MCU or other system device.

When EN is set high (or on rising edge of EN2 and then confirmed by EN = 1), the supply regulators are activated and the 13.56-MHz oscillator is started. When the supplies are settled and the oscillator frequency is stable, the SYS_CLK output is switched from the auxiliary frequency of 60 kHz to the selected frequency derived from the crystal oscillator. At this time, the reader is ready to communicate and perform the required tasks. The control system (MCU) can then write appropriate bits to the Chip Status Control register (address 0x00) and select the operation mode.

The standby mode (bit 7 = 1 in register 0x00) is the active mode with the lowest current consumption. The reader can recover from this mode to full operation in 100 µs.

The active mode with RF section disabled (bit 5 = 0 and bit 1 = 0 in register 0x00) is the next active mode with low power consumption. The reader is capable of recovering from this mode to full operation in 25 µs.

The active mode with only the RF receiver section active (bit 1 = 1 in register 0x00) can be used to measure the external RF field (see Section 6.3.1) if reader-to-reader anticollision is implemented.

The active mode with the entire RF section active (bit 5 = 1 in register 0x00) is the normal mode used for transmit and receive operations.

Timing Diagrams

Figure 6-2 shows an oscilloscope trace of chip power up.

Figure 6-3 shows an oscilloscope trace of chip enable to clock start with EN2 low and EN high.

Figure 6-4 shows an oscilloscope trace of chip enable to clock start with EN2 high and EN low.

TRF7960 TRF7961 c001_lou186.png Figure 6-2 Chip Power Up [VIN (Blue) to Crystal Start (Red)]
TRF7960 TRF7961 c002_lou186.png Figure 6-3 Chip Enable to Clock Start, EN2 Low and EN High (Blue) to Start of System Clock (Red)
TRF7960 TRF7961 c003_lou186.png Figure 6-4 Chip Enable to Clock Start, EN2 High and EN Low (Blue) to Start of System Clock (Red)

Receiver – Analog Section

The TRF796x has two receiver inputs, RX_IN1 (pin 8) and RX_IN2 (pin 9). The two inputs are connected to an external filter to ensure that AM modulation from the tag is available on at least one of the two inputs. The external filter provides a 45° phase shift for the RX_IN2 input to allow further processing of a received PM-modulated signal (if it appears) from the tag. This architecture eliminates any possible communication holes that may occur from the tag to the reader.

The two RX inputs are multiplexed to two receiver channels: the main receiver and the auxiliary receiver. Receiver input multiplexing is controlled by control bit B3 (pm_on) in the Chip Status Control register (address 0x00). The main receiver is composed of an RF-detection stage, gain, filtering with AGC, and a digitizing stage whose output is connected to the digital processing block. The main receiver also has an RSSI measuring stage, which measures the strength of the demodulated signal.

The primary function of the auxiliary receiver is to measure the RSSI of the modulation signal. It also has similar RF-detection, gain, filtering with AGC, and RSSI blocks.

The default setting is RX_IN1 connected to the main receiver and RX_IN2 connected to the auxiliary receiver (bit pm_on = 0). When a response from the tag is detected by the RSSI, values on both inputs are measured and stored in the RSSI Level register (address 0x0F). The control system reads the RSSI values and switches to the stronger receiver input (RX_IN1 or RX_IN2 by setting pm_on = 1).

The receiver input stage is an RF level detector. The RF amplitude level on RX_IN1 and RX_IN2 inputs should be approximately 3 VPP for a VIN supply level greater than 3.3 V. If the VIN level is lower, the RF input peak-to-peak voltage level should not exceed the VIN level. VIN is the main supply voltage to the device at pin 2.

The first gain and filtering stage following the RF-envelope detector has a nominal gain of 15 dB with an adjustable band-pass filter. The band-pass filter has adjustable 3-dB frequency steps (100 kHz to 400 kHz for high pass and 600 kHz to 1500 kHz for low pass). Following the band-pass filter is another gain-and-filtering stage with a nominal gain of 8 dB and with frequency characteristics identical to the first stage.

The internal filters are configured automatically, with internal presets for each new selection of a communication standard in the ISO Control register (address 0x01). If required, additional fine-tuning can be accomplished by writing directly to the RX Special Setting register (address 0x0A). Table 6-22 lists the bits of the RX Special Settings register (address 0x0A) that control the receiver analog section.

Received Signal Strength Indicator (RSSI)

The RSSI measurement block measures the demodulated signal (except in the case of a direct command for RF-amplitude measurement; see Section 6.5). The measuring system latches the peak value, so the RSSI level can be read after the end of the receive packet. The RSSI register values reset with every transmission by the reader. This allows an updated RSSI measurement for each new tag response.

Table 6-7 and Table 6-8 list the correlation between the RF input level and RSSI designation levels on RX_IN1 and RX_IN2.

Table 6-7 compares the RSSI level and the RSSI bit value. The RSSI has seven levels (3 bits each) with 4-dB increments. The input level is the peak-to-peak modulation level of the RF signal as measured on one side envelope (positive or negative).

Table 6-7 RSSI Level Versus Register Bit Value

RSSI 1 2 3 4 5 6 7
Input level 2 mVpp 3.2 mVpp 5 mVpp 8 mVpp 13 mVpp 20 mVpp 32 mVpp

As an example, from Table 6-8, let B2 = 1, B1 = 1, B0 = 0. This yields an RSSI value of 6. From Table 6-7 a bit value of 6 indicates an RSSI level of 20 mVpp.

Table 6-8 RSSI Bit Value and Oscillator Status Register (0x0F)

BIT SIGNAL FUNCTION COMMENTS
B7 Unused
B6 osc_ok Crystal oscillator stable
B5 rssi_x2 Most significant bit (MSB) of auxiliary receiver RSSI 4 dB per step
B4 rssi_x1 Auxiliary receiver RSSI
B3 rssi_x1 Least significant bit (LSB) of auxiliary receiver RSSI
B2 rssi_2 MSB of main receiver RSSI 4 dB per step
B1 rssi_1 Main receiver RSSI
B0 rssi_0 LSB of main receiver RSSI

Receiver – Digital Section

The received subcarrier is digitized to form a digital representation of the modulated RF envelope. This digitized signal is applied to digital decoders and framing circuits for further processing.

The digital part of the receiver consists of two sections, which partly overlap. The first section consists of the bit decoders for the various protocols, and the second section consists of the framing logic. The bit decoders convert the subcarrier coded signal to a bit stream and also to the data clock. Thus, the subcarrier-coded signal is transformed to serial data, and the data clock is extracted. The decoder logic is designed for maximum error tolerance. This enables the decoders to successfully decode even partly corrupted (due to noise or interference) subcarrier signals.

In the framing section, the serial bit stream data is formatted in bytes. In this process, special signals like the start of frame (SOF), end of frame (EOF), start of communication, and end of communication are automatically removed. The parity bits and CRC bytes are checked and also removed. The end result is clean or raw data, which is sent to the 12-byte FIFO register where it can be read by the external microcontroller system.

The start of the receive operation (successfully received SOF) sets the flags in the IRQ Status register. The end of the receive operation is indicated to the external system (MCU) by sending an interrupt request (pin 13, IRQ). If the receive data packet is longer than 8 bytes, an interrupt is sent to the MCU when the received data occupies 75% of the FIFO capacity to signal that the data should be removed from the FIFO. Use the FIFO Status register (0x1C) to provide the number of bytes that should be clocked out during the actual FIFO read.

If any error in data format, parity, or CRC is detected, the external system is notified of the error by an interrupt-request pulse. The source condition of the interrupt-request pulse is available in the IRQ Status register (address 0x0C) (see Table 6-24).

The ISO Control register (address 0x01) is the primary control for the digital part of the receiver. By writing to this register, the application selects the protocol to be used. With each new write in this register, the default presets are loaded in all related registers, so no further adjustments in other registers are typically needed for proper operation.

Table 6-12 describes the coding of the ISO Control register. The TRF7961 does not include the ISO/IEC 14443 functionality; therefore, the features and commands for this protocol are not functional for the TRF7961.

The framing section also supports bit-collision detection as specified in ISO/IEC 14443 A and ISO/IEC 15693. When a bit collision is detected, an interrupt request is sent and a flag is set in the IRQ Status register. For ISO/IEC 14443 A specifically, the position of the bit collision is written in two registers: partly in the Collision Position register (0x0E) and partly in the Collision Position and Interrupt Mask register (0x0D) (bits B6 and B7). The collision position is presented as a sequential bit number, where the count starts immediately after the start bit. For example, the collision in the first bit of the UID would give the value 00 0001 0000 in the collision position registers. The count starts with 0, and the first 16 bits are the command code and the NVB byte (the NVB byte is the number of valid bits).

The receive section also has two timers. The RX wait time timer is controlled by the value in the RX Wait Time register (address 0x08). This timer defines the time after the end of the transmit operation in which the receive decoders are not active (held in reset state). This prevents incorrect detections resulting from transients following the transmit operation. The value of the RX Wait Time register defines this time in increments of 9.44 µs. This register is preset at every write to ISO Control register (address 0x01) according to the minimum tag-response time defined by each standard.

The RX no response timer is controlled by the RX No Response Wait Time register (address 0x07). This timer measures the time from the start of slot in the anticollision sequence until the start of tag response. If there is no tag response in the defined time, an interrupt request is sent and a flag is set in IRQ Status Control register. This enables the external controller to be relieved of the task of detecting empty slots. The wait time is stored in the register in increments of 37.76 µs. This register is also preset, automatically, for every new protocol selection.

Transmitter

The transmitter section consists of the 13.56-MHz oscillator, digital protocol processing, and RF output stage.

Transmitter – Analog Section

The 13.56-MHz crystal oscillator (connected to pins 31 and 32) directly generates the RF for the RF output stage. It also generates the clock signal for the digital section and the clock signal output on SYS_CLK (pin 27), which can be used by an external MCU system.

During partial power-down mode (EN = 0, EN2 = 1), the frequency of SYS_CLK is 60 kHz. During normal reader operation, SYS_CLK can be programmed by bits B4 and B5 in the Modulator and SYS_CLK Control register (address 0x09); available clock frequencies are 13.56 MHz, 6.78 MHz, or 3.39 MHz.

Table 6-9 lists the recommendations for the reference crystal (HC49U).

Table 6-9 Crystal Recommendations

PARAMETER SPECIFICATION
Frequency 13.560000 MHz
Mode of operation Fundamental
Type of resonance Parallel
Frequency tolerance ±20 ppm
Aging <5 ppm/year
Operation temperature range –40°C to 85°C
Equivalent series resistance 50 Ω, minimum

NOTE

The value of the two external shunt capacitors on the crystal oscillator is calculated based on the specified load capacitance of the crystal. The external capacitors (connected to the OSC pins 30 and 31), are calculated as two capacitors in series plus CS (the internal I/O capacitance of the oscillator gate plus PCB stray capacitance). The stray capacitance (CS) can be estimated at 5 ±2 pF (typical).

As an example, given a crystal with a required load capacitance (CL) of 18 pF,

CL = ((C1 × C2) / (C1 + C2)) + CS

18 pF = ((27 pF × 27 pF) / (27 pF + 27 pF)) + 4.5 pF

From this example, 18-pF capacitors would be placed on pins 30 and 31 to ensure proper crystal oscillator operation.

The transmit power level is selectable as either half power of 100 mW (20 dBm) or full power of 200 mW (23 dBm) when configured for 5-V automatic operation. The transmit output impedance is 8 Ω when configured for half power and 4 Ω when configured for full power. Selection of the transmit power level is set by bit B4 (rf_pwr) in the Chip Status Control register (see Table 6-11). When configured for 3-V automatic operation, the transmit power level is typically selectable as either 33 mW (15 dBm) in half-power mode or 70 mW (18 dBm) in full-power mode (VDD_RF at 3.3 V). Lower operating voltages result in reduced transmit power levels.

In typical operation, the transmit modulation is configured by the selected ISO Control register (address 0x01). External control of the transmit modulation is possible by setting the ISO Control register (address 0x01) to direct mode. While in direct mode, the transmit modulation is set by the ASK/OOK pin (pin 12). External control of the modulation type is enabled by setting B6 = 1 (en_ook_p) in the Modulator and SYS_CLK Control register (address 0x09). ASK modulation depth is controlled by bits B0, B1, and B2 in the Modulator and SYS_CLK Control register (address 0x09). The range of the ASK modulation is 7% to 30%, or 100% (OOK).

Table 6-21 describes the coding of the Modulator and SYS_CLK Control register.

The length of the modulation pulse is defined by the protocol selected in the ISO Control register. With a high-Q antenna, the modulation pulse is typically prolonged, and the tag detects a longer pulse than intended. For such cases, the modulation pulse length can be corrected by using the TX Pulse Length register. If the register contains all zeros, then the pulse length is governed by the protocol selection. If the register contains a value other than 00h, the pulse length is equal to the value of the register in 73.7-ns increments. This means the range of adjustment is 73.7 ns to 18.8 µs.

Transmitter – Digital Section

The digital portion of the transmitter is very similar to that of the receiver. Before beginning data transmission, the FIFO should be cleared with a Reset command (0x0F). Data transmission is initiated with a selected command (see Table 6-31). The MCU then commands the reader to do a continuous Write command (3Dh, see Table 6-33) starting from register 1Dh. Data written into register 1Dh is the TX Length Byte1 (upper and middle nibbles), while the following byte in register 1Eh is the TX Length Byte2 (lower nibble and broken byte length). The TX byte length determines when the reader sends the EOF byte. After the TX length bytes, FIFO data is loaded in register 1Fh with byte storage locations 0 to 11. Data transmission begins automatically after the first byte is written into the FIFO. The TX Length bytes and FIFO can be loaded with a continuous-write command because the addresses are sequential.

If the data length is longer than the allowable size of the FIFO, the external system (MCU) is warned when the majority of data from the FIFO has already been transmitted by sending an interrupt request with a flag in the IRQ register signaling FIFO low or high status. The external system should respond by loading the next data packet into the FIFO.

At the end of the transmit operation, the external system is notified by another interrupt request with a flag in the IRQ register that signals the end of TX.

The TX Length register also supports incomplete bytes transmitted. The high 2 nibbles in register 0x1D and the nibble composed of bits B4 to B7 in register 0x1E store the number of complete bytes to be transmitted. Bit 0 (in register 0x1E) is a flag that signals the presence of additional bits to be transmitted that do not form a complete byte. The number of bits are stored in bits B1 to B3 of the same register (0x1E).

The protocol is selected by the ISO Control register (address 0x01), which also selects the receiver protocol. As defined by the selected protocol, the reader automatically adds all the special signals, like start of communication, end of communication, SOF, EOF, parity bits, and CRC bytes. The data is then coded to the modulation pulse level and sent to the modulation control of the RF output stage. This means that the external system is only required to load the FIFO with data, and all the low-level coding is done automatically. Also, all registers used in transmission are automatically preset to the optimum value when a new selection is entered into the ISO Control register.

Some protocols have options, and two registers are provided to select the TX protocol options. The first register is ISO14443B TX Options (address 0x02). This register controls the SOF and EOF selection and EGT (extra guard time) selection for the ISO/IEC 14443 B protocol (see Table 6-14)

The second register controls the ISO/IEC 14443 high-bit-rate options. This register enables the use of different bit rates for RX and TX operations in the ISO/IEC 14443 high bit-rate protocol. Additionally, it also selects the parity system for the ISO/IEC 14443 A high-bit-rate selection (see Table 6-15).

The transmit section also has a timer that can be used to start the transmit operation at a precise time interval from a selected event. This is necessary if the tag requires a reply in an exact window of time following the tag response. The TX timer uses two registers (addresses 0x04 and 0x05). In first register (address 0x04), two bits (B7 and B6) define the trigger conditions. The remaining 6 bits are the upper bits and the 8 bits in register address 0x05 are lower bits, which are preset to the counter. The increment is 590 ns and the range of this counter is from 590 ns to 9.7 ms. See Table 6-16 for the bit definitions (trigger conditions).

Direct Mode

Direct mode supports two configurations:

Direct mode 0 (bit 6 = 0 in the ISO Control register) enables use of only the front-end functions of the reader, bypassing the protocol implementation in the reader. For transmit functions, the application has direct access to the transmit modulator through the MOD pin (pin 14). On the receive side, the application has direct access to the subcarrier signal (digitized RF envelope signal) on I/O_6 (pin 23).

Direct mode 1 (bit 6 = 1 in the ISO Control register) uses the subcarrier signal decoder of the selected protocol (as defined in the ISO Control register). This means that the receive output is not the subcarrier signal but the decoded serial bit stream and bit clock signals. The serial data is available on I/O_6 (pin 23) and the bit clock is available on I/O_5 (pin 22). The transmit side is identical; the application has direct control over the RF modulation through the MOD input. This mode is provided so that the application can implement a protocol that has the same bit coding as one of the protocols implemented in the reader, but needs a different framing format.

To use direct mode, first select the direct mode to enter by writing B6 in the ISO Control register. This bit determines if the receive output is the direct subcarrier signal (B6 = 0) or the serial data of the selected decoder. If B6 = 1, also define which protocol should be used for bit decoding by writing the appropriate setting in the ISO Control register.

The reader actually enters the direct mode when B6 (direct) is set to 1 in the Chip Status Control register. Direct mode starts immediately. The write command should not be terminated with a stop condition (see communication protocol), because the stop condition terminates the direct mode and clears B6. This is necessary as the direct mode uses one or two I/O pins (I/O_6, I/O_5). Standard parallel communication is not possible in direct mode. Sending a stop condition terminates direct mode.

Figure 6-5 shows mode 0 and mode 1 in direct mode.

  • In mode 0, the reader is used as an AFE only, and protocol handling is bypassed.
  • In mode 1, framing is not done, but SOF and EOF are present. This allows for a user-selectable framing level based on an existing ISO standard.

In mode 2 (standard mode), data is ISO-standard formatted. SOF, EOF, and error checking are removed, so the microprocessor receives only bytes of raw data through a 12-byte FIFO.

TRF7960 TRF7961 direct_mode_lou186.gif Figure 6-5 User-Configurable Modes

Register Preset

After power up and the EN pin low-to-high transition, the reader is in the default mode. The default configuration is ISO/IEC 15693, single subcarrier, high data rate, 1-out-of-4 operation. The low-level option registers (0x02 to 0x0B) are automatically set to adapt the circuitry optimally to the appropriate protocol parameters.

When entering another protocol (writing to the ISO Control register [0x01]), the low-level option registers (0x02 to 0x0B) are automatically configured to the new protocol parameters.

After selecting the protocol, it is possible to change some low-level register contents if needed. However, changing to another protocol and then back, reloads the default settings, and the application must reload the custom settings.

The Clo1 and Clo0 bits in register 0x09, which define the microcontroller frequency available on the SYS_CLK pin, are the only two bits in the configuration registers that are not cleared during protocol selection.

Register Descriptions

Table 6-10 lists the registers by address.

Table 6-10 Register Address Space

ADDRESS REGISTER READ/WRITE DETAILS
Main Control Registers
0x00 Chip status control R/W Table 6-11
0x01 ISO control R/W Table 6-12
Protocol Subsetting Registers
0x02 ISO14443B TX options R/W Table 6-14
0x03 ISO14443A high bit rate options R/W Table 6-15
0x04 TX timer setting, H-byte R/W Table 6-16
0x05 TX timer setting, L-byte R/W Table 6-17
0x06 TX pulse-length control R/W Table 6-18
0x07 RX no response wait R/W Table 6-19
0x08 RX wait time R/W Table 6-20
0x09 Modulator and SYS_CLK control R/W Table 6-21
0x0A RX special setting R/W Table 6-22
0x0B Regulator and I/O control R/W Table 6-23
0x16 Unused NA
0x17 Unused NA
0x18 Unused NA
0x19 Unused NA
Status Registers
0x0C IRQ status R Table 6-24
0x0D Collision position and interrupt mask register R/W Table 6-25
0x0E Collision position R Table 6-26
0x0F RSSI levels and oscillator status R Table 6-27
FIFO Registers
0x1C FIFO status R Table 6-28
0x1D TX length byte1 R/W Table 6-29
0x1E TX length byte2 R/W Table 6-30
0x1F FIFO I/O register R/W

Control Registers – Main Configuration Registers

Table 6-11 describes the Chip Status Control register. This register controls the power mode, RF on or off, and AM or PM. The register default is 0x01 and is reset at EN = L or POR = H.

Table 6-11 Chip Status Control Register (Address = 00h)

BIT BIT NAME FUNCTION COMMENTS
B7 stby 1 = Standby mode
0 = Active mode
Standby mode keeps regulators and oscillator running when en_rec = L and en_tx = L.
B6 direct 1 = Received subcarrier signal (decoders bypassed)
0 = Received decoded signal from selected decoder
The modulation control is direct through MOD input. The receiver subcarrier signal is on I/0_6.
B5 rf_on 1 = RF output active
0 = RF output not active
When B5 = 1, the RF field is active.
B4 rf_pwr 1 = Half output power
0 = Full output power
1 = RF driver at 8 Ω
0 = RF driver at 4 Ω
B3 pm_on 1 = RX_IN2
0 = RX_IN1
1 = Selects PM signal input
0 = Selects AM signal input
B2 Reserved
B1 rec_on 1 = Receiver enable for external field measurement
Receiver and oscillator are enabled; intended for external field measurement.
B0 vrs5_3 1 = 5-V operation (VIN)
0 = 3-V operation (VIN)
Selects the VDD_RF range: 5 V (4.3 V to 5 V) or 3 V (2.7 V to 3.4 V)

Table 6-12 describes the ISO Control register. This register controls the ISO selection. The register default is 0x02, which is ISO/IEC 15693 high bit rate, one subcarrier, 1 out of 4. The default is reset at EN = L or POR = H.

Table 6-12 ISO Control Register (Address = 01h)

BIT BIT NAME FUNCTION COMMENTS
B7 rx_crc_n Receiving without CRC 1 = No RX CRC
0 = RX CRC
B6 dir_mode Direct mode type 0 = Output is subcarrier data.
1 = Output is bit stream (I/O_6) and bit clock (I/O_5) from decoder selected by ISO bits
B5 rfid RFID mode Always set to 0.
B4 iso_4 RFID mode See Table 6-13.
B3 iso_3
B2 iso_2
B1 iso_1
B0 iso_0

Table 6-13 RFID Mode Selections

Iso_4 Iso_3 Iso_2 Iso_1 Iso_0 PROTOCOL REMARKS
0 0 0 0 0 ISO/IEC 15693 low bit rate, 6.62 kbps, one subcarrier, 1 out of 4
0 0 0 0 1 ISO/IEC 15693 low bit rate, 6.62 kbps, one subcarrier, 1 out of 256
0 0 0 1 0 ISO/IEC 15693 high bit rate, 26.48 kbps, one subcarrier, 1 out of 4 Default for reader
0 0 0 1 1 ISO/IEC 15693 high bit rate, 26.48 kbps, one subcarrier, 1 out of 256
0 0 1 0 0 ISO/IEC 15693 low bit rate, 6.67 kbps, double subcarrier, 1 out of 4
0 0 1 0 1 ISO/IEC 15693 low bit rate, 6.67 kbps, double subcarrier, 1 out of 256
0 0 1 1 0 ISO/IEC 15693 high bit rate, 26.69 kbps, double subcarrier, 1 out of 4
0 0 1 1 1 ISO/IEC 15693 high bit rate, 26.69 kbps, double subcarrier, 1 out of 256
0 1 0 0 0 ISO/IEC 14443 A bit rate, 106 kbps RX bit rate when TX bit rate is different from RX (see Table 6-15)
0 1 0 0 1 ISO/IEC 14443 A high bit rate, 212 kbps
0 1 0 1 0 ISO/IEC 14443 A high bit rate, 424 kbps
0 1 0 1 1 ISO/IEC 14443 A high bit rate, 848 kbps
0 1 1 0 0 ISO/IEC 14443 B bit rate, 106 kbps RX bit rate when TX bit rate is different from RX (see Table 6-15)
0 1 1 0 1 ISO/IEC 14443 B high bit rate, 212 kbps
0 1 1 1 0 ISO/IEC 14443 B high bit rate, 424 kbps
0 1 1 1 1 ISO/IEC 14443 B high bit rate, 848 kbps
1 0 0 1 1 Tag-it

Control Registers – Sublevel Configuration Registers

Table 6-14 describes the ISO14443B TX Options register. This register selects the ISO subsets for ISO/IEC 14443 B transmit. The register default is 0x00 and is reset at POR = H or EN = L.

Table 6-14 ISO14443B TX Options Register (Address = 02h)

BIT BIT NAME FUNCTION COMMENTS
B7 egt2 TX EGT time select MSB This 3-bit code defines the number of etu (0 to 7) that separate two characters. ISO/IEC 14443 B TX only.
B6 egt1 TX EGT time select
B5 egt0 TX EGT time select LSB
B4 eof_l0 1 = EOF, 0 length 11 etu ISO/IEC 14443 B TX only
0 = EOF, 0 length 10 etu
B3 sof_l1 1 = SOF, 1 length 03 etu
0 = SOF, 1 length 02 etu
B2 sof _l0 1 = SOF, 0 length 11 etu
0 = SOF, 0 length 10 etu
B1 l_egt 1 = EGT after each byte
0 = EGT after last byte is omitted
B0 Unused

Table 6-15 describes the ISO14443A High-Bit-Rate Options register. The register default is 0x00 and is rest at POR = H or EN = L and at each write to the ISO Control register.

Table 6-15 ISO14443A High-Bit-Rate Options Register (Address = 03h)

BIT BIT NAME FUNCTION COMMENTS
B7 dif_tx_br TX bit rate different from RX bit rate enable Valid for ISO/IEC 14443 A or B high bit rate
B6 tx_br1 TX bit rate tx_br1 = 0, tx_br = 0: 106 kbps
tx_br1 = 0, tx_br = 1: 212 kbps
tx_br1 = 1, tx_br = 0: 424 kbps
tx_br1 = 1, tx_br = 1: 848 kbps
B5 tx_br0
B4 parity-2tx 1 = Parity odd except last byte, which is even for TX For ISO/IEC 14443 A high bit rate, coding and decoding
B3 parity-2rx 1 = Parity odd except last byte, which is even for RX
B2 Unused
B1 Unused
B0 Unused

Table 6-16 describes the TX Timer H-Byte register. The register default is 0xC2 and is reset at POR = H or EN = L and at each write to the ISO Control register.

Table 6-16 TX Timer H-Byte Register (Address = 04h)

BIT BIT NAME FUNCTION COMMENTS
B7 Tm_st1 Timer start condition tm_st1 = 0, tm_st0 = 0: Beginning of TX SOF
tm_st1 = 0, tm_st0 = 1: End of TX SOF
tm_st1 = 1, tm_st0 = 0: Beginning of RX SOF
tm_st1 = 1, tm_st0 = 1: End of RX SOF
B6 Tm_st0
B5 Tm_lengthD Timer length. MSB is B5.
B4 Tm_lengthC
B3 Tm_lengthB
B2 Tm_lengthA
B1 Tm_length9
B0 Tm_length8

Table 6-17 describes the TX Timer L-Byte register. The register default is 0x00 and is reset at POR = H or EN = L and at each write to the ISO Control register.

Table 6-17 TX Timer L-Byte Register (Address = 05h)

BIT BIT NAME FUNCTION COMMENTS
B7 Tm_length7 Timer length. MSB is B7. Defines the time when delayed transmission is started. RX wait range is 590 ns to 9.76 ms (1 to 16383), and the step size is 590 ns.
All bits low (00) = Timer is disabled (preset for all protocols)
B6 Tm_length6
B5 Tm_length5
B4 Tm_length4
B3 Tm_length3
B2 Tm_length2
B1 Tm_length1
B0 Tm_length0

Table 6-18 describes the TX Pulse Length Control register. This register controls the length of TX pulse. The register default is 0x00 and is reset at POR = H or EN = L and at each write to the ISO Control register.

Table 6-18 TX Pulse Length Control Register (Address = 06h)

BIT BIT NAME FUNCTION COMMENTS
B7 Pul_p2 Pulse length. MSB is B7. The pulse range is 73.7 ns to 18.8 µs (1 to 255), and the step size is 73.7 ns.

All bits low (00) = Pulse length control is disabled

Presets are:

9.44 µs for ISO/IEC 15693

11 µs for Tag-it

2.36 µs for ISO/IEC 14443 A at 106 kbps

1.4 µs for ISO/IEC 14443 A at 212 kbps

737 ns for ISO/IEC 14443 A at 424 kbps

442 ns for ISO/IEC 14443 A at 848 kbps

B6 Pul_p1
B5 Pul_p0
B4 Pul_c4
B3 Pul_c3
B2 Pul_c2
B1 Pul_c1
B0 Pul_c0

Table 6-19 describes the RX No Response Wait Time register. This register defines the time when a no response interrupt is sent. The default is 0x0E and is reset at POR = H or EN = L and at each write to the ISO Control register.

Table 6-19 RX No Response Wait Time Register (Address = 07h)

BIT BIT NAME FUNCTION COMMENTS
B7 NoResp7 No response. MSB is B7. Defines the time when the no response interrupt is sent. Time starts from the end of TX EOF. RX no response wait range is 37.76 µs to 9628 µs (1 to 255), and step size is 37.76 µs.

Presets are:

755 µs for ISO/IEC 15693

1812 µs for ISO/IEC 15693 low data rate

604 µs for Tag-it

529 µs for all other protocols

B6 NoResp6
B5 NoResp5
B4 NoResp4
B3 NoResp3
B2 NoResp2
B1 NoResp1
B0 NoResp0

Table 6-20 describes the RX Wait Time register. This register defines the time after TX EOF when the RX input is disregarded. The default is 0x1F and is reset at POR = H or EN = L and at each write to the ISO Control register.

Table 6-20 RX Wait Time Register (Address = 08h)

BIT BIT NAME FUNCTION COMMENTS
B7 Rxw7 RX wait Defines the time during which the RX input is ignored. Starts from the end of TX EOF. RX wait range is 9.44 µs to 2407 µs (1 to 255), and step size is 9.44 µs.

Presets are:

293 µs for ISO/IEC 15693

66 µs for ISO/IEC 14443 A and B

180 µs for Tag-it

B6 Rxw6
B5 Rxw5
B4 Rxw4
B3 Rxw3
B2 Rxw2
B1 Rxw1

Table 6-21 describes the Modulator and SYS_CLK Control register. This register controls the modulation depth, modulation input, and ASK/OOK pin control. The default is 0x11 and is reset at POR = H or EN = L and at each write to the ISO Control register, except for the Clo1 and Clo0 bits.

Table 6-21 Modulator and SYS_CLK Control Register (Address = 09h)

BIT BIT NAME FUNCTION COMMENTS
B7 Unused
B6 en_ook_p 1 = Enables external selection of ASK or OOK modulation Valid only when ISO control register (0x01) is configured to direct mode
B5 Clo1 SYS_CLK output frequency. MSB is B5. Clo1 Clo0 SYS_CLK Output
0 0 Disabled
0 1 3.3 MHz
B4 Clo0 1 0 6.78 MHz
1 1 13.56 MHz
B3 en_ana 1 = Enables analog output on the ASK/OOK pin (pin 12) For test and measurement
B2 Pm2 Modulation depth. MSB is B2. Pm2 Pm1 Pm0 Modulation Type and Percentage
0 0 0 ASK 10%
0 0 1 OOK (100%)
B1 Pm1 0 1 0 ASK 7%
0 1 1 ASK 8.5%
1 0 0 ASK 13%
B0 Pm0 1 0 1 ASK 16%
1 1 0 ASK 22%
1 1 1 ASK 30%

Table 6-22 describes the RX Special Setting register. This register sets the gains and filters directly. The default is 0x40 and is reset at POR = H or EN = L and at each write to the ISO Control register.

Table 6-22 RX Special Setting Register (Address = 0Ah)

BIT BIT NAME FUNCTION COMMENTS
B7 C212 Band-pass filter of 110 kHz to 570 kHz Appropriate for 212-kHz subcarrier system
B6 C424 Band-pass filter of 200 kHz to 900 kHz Appropriate for 424-kHz subcarrier used in ISO/IEC 15693 and Tag-it
B5 M848 Band-pass filter of 450 kHz to 1.5 MHz Appropriate for Manchester-coded 848-kHz subcarrier used in ISO/IEC 14443 A
B4 hbt Band-pass filter of 100 kHz to 1.5 MHz
Gain reduced for 7 dB
Appropriate for highest bit rate (848 kbps) used in high-bit-rate ISO/IEC 14443
B3 gd1 01 = Gain reduction for 5 dB
10 = Gain reduction for 10 dB
11 = Gain reduction for 15 dB
Sets the RX gain reduction
B2 gd2
B1 Reserved
B0 Reserved

Table 6-23 describes the Regulator and I/O Control register. This register controls the three voltage regulators. The default is 0x87 and is reset at POR = H or EN = L.

Table 6-23 Regulator and I/O Control Register (Address = 0Bh)

BIT BIT NAME FUNCTION COMMENTS
B7 auto_reg 0 = Setting regulator by option bits (vrs3_5 and vrs2, vrs1, and vrs0)
1 = Automatic setting
Automatic system sets VDD_RF = (VIN – 250 mV) and sets
VDD_A = VDD_X = (VIN – 250 mV) but not higher than 3.4 V.
B6 en_ext_pa Support for external power amplifier Receiver inputs accept externally demodulated subcarrier, OOK pin becomes modulation output for external amplifier.
B5 io_low 1 = Enable low peripheral communication voltage When high, the output resistance of logic outputs is decreased. Should be set high when VDD_I/O voltage is below 2.7 V.
B4 Unused Default is low.
B3 Unused Default is low.
B2 vrs2 Voltage set. MSB is B2. vrs3_5 = L: VDD_RF, VDD_A, VDD_X range 2.7 V to 3.4 V
B1 vrs1
B0 vrs0

Status Registers

Table 6-24 describes the IRQ Status register. This register displays the cause of IRQ and TX and RX status. The default is 0x00 and is reset at POR = H or EN = L and at each write to the ISO Control register. The register is also automatically set to default at the end of a read phase. This reset also removes the IRQ flag.

Table 6-24 IRQ Status Register (Address = 0Ch)

BIT BIT NAME FUNCTION COMMENTS
B7 Irq_tx IRQ set due to end of TX Signals that TX is in progress. The flag is set at the start of TX but the interrupt request is sent when TX is finished.
B6 Irg_srx IRQ set due to RX start Signals that RX SOF was received and RX is in progress. The flag is set at the start of RX but the interrupt request is sent when RX is finished.
B5 Irq_fifo Signals the FIFO is 1/3 > FIFO > 2/3 Signals FIFO high or low (less than 4 or more than 8)
B4 Irq_err1 CRC error Indicates receive CRC error
B3 Irq_err2 Parity error Indicates parity error
B2 Irq_err3 Byte framing or EOF error Indicates framing error
B1 Irq_col Collision error For ISO/IEC 14443 A and ISO/IEC 15693 single subcarrier
B0 Irq_noresp No response interrupt Signal to MCU that next slot command can be sent

Table 6-25 describes the Collision Position and Interrupt Mask register. The default is 0x3E and is reset at POR = H and EN = L. Collision bits are reset automatically after a read operation.

Table 6-25 Collision Position and Interrupt Mask Register (Address = 0Dh)

BIT BIT NAME FUNCTION COMMENTS
B7 Col9 Bit position of collision MSB Supported: ISO/IEC 15693, single subcarrier, and ISO/IEC 14443 A
B6 Col8 Bit position of collision
B5 En_irq_fifo Interrupt enable for FIFO
B4 En_irq_err1 Interrupt enable for CRC
B3 En_irq_err2 Interrupt enable for Parity
B2 En_irq_err3 Interrupt enable for Framing error or EOF
B1 En_irq_col Interrupt enable for collision error
B0 En_irq_noresp Enables no-response interrupt

Table 6-26 describes the Collision Position register. This register displays the bit position of collision or error. The default is 0x00 and is reset at POR = H and EN = L. Collision bits are reset automatically after a read operation.

Table 6-26 Collision Position Register (Address = 0Eh)

BIT BIT NAME FUNCTION COMMENTS
B7 Col7 Bit position of collision. MSB is B7. Supports ISO/IEC 15693 single subcarrier and ISO/IEC 14443 A. In other protocols, it shows the bit position of error, either frame, SOF-EOF, parity, or CRC error.
B6 Col6
B5 Col5
B4 Col4
B3 Col3
B2 Col2
B1 Col1
B0 Col0

Table 6-27 describes the RSSI Levels and Oscillator Status register. This register reports the signal strength on both reception channels and RF amplitude during RF-off state. The RSSI values are valid from reception start until the start of the next transmission.

Table 6-27 RSSI Levels and Oscillator Status Register (Address = 0Fh)

BIT BIT NAME FUNCTION COMMENTS
B7 Unused
B6 Oscok Crystal oscillator stable indicator
B5 rssi_x2 RSSI value of auxiliary channel (4 dB per step). MSB is B5. Auxiliary channel is PM by default. It can be set to AM with option bit B3 of the Chip State Control register (00h).
B4 rssi_x1
B3 rssi_x0
B2 rssi_2 RSSI value of active channel (4 dB per step). MSB is B2. Active channel is AM by default. It can be set to PM with option bit B3 of the Chip State Control register (00h).
B1 rssi_1
B0 rssi_0

FIFO Control Registers

Table 6-28 describes the FIFO Status register. This register reports the low nibbles of complete bytes to be transferred through FIFO, information about a broken byte, and the number of bits to be transferred from it.

Table 6-28 FIFO Status Register (Address = 1Ch)

BIT BIT NAME FUNCTION COMMENTS
B7 RFU Set to low Reserved for future use
B6 Fhil FIFO level high Indicates that 9 bytes are in the FIFO (for RX)
B5 Flol FIFO level low Indicates that 3 bytes are in the FIFO (for TX)
B4 Fove FIFO overflow error Too much data was written to the FIFO
B3 Fb3 FIFO bytes fb[3] Bits B0:B3 indicate how many bytes that are loaded in FIFO were not read out yet. Reports (N – 1) number of bytes; for example, if 8 bytes are in the FIFO, this number is 7.
B2 Fb2 FIFO bytes fb[2]
B1 Fb1 FIFO bytes fb[1]
B0 Fb0 FIFO bytes fb[0]

Table 6-29 describes the TX Length Byte1 register. This register reports the high 2 nibbles of complete bytes to be transferred through the FIFO. The default is 0x00 and is reset at POR and EN = 0. It is also automatically reset at TX EOF.

Table 6-29 TX Length Byte1 Register (Address = 1Dh)

BIT BIT NAME FUNCTION COMMENTS
B7 Txl11 Number of complete byte bn[11] High nibble of complete bytes to be transmitted
B6 Txl10 Number of complete byte bn[10]
B5 Txl9 Number of complete byte bn[9]
B4 Txl8 Number of complete byte bn[8]
B3 Txl7 Number of complete byte bn[7] Middle nibble of complete bytes to be transmitted
B2 Txl6 Number of complete byte bn[6]
B1 Txl5 Number of complete byte bn[5]
B0 Txl4 Number of complete byte bn[4]

Table 6-30 describes the TX Length Byte2 register. This register reports the low nibble of complete bytes to be transferred through the FIFO, information about a broken byte, and the number of bits to be transferred from it. The default is 0x00 and is reset at POR and EN = 0. It is also automatically reset at TX EOF.

Table 6-30 TX Length Byte2 Register (Address = 1Eh)

BIT BIT NAME FUNCTION COMMENTS
B7 Txl3 Number of complete byte bn[3] Low nibble of complete bytes to be transmitted
B6 Txl2 Number of complete byte bn[2]
B5 Txl1 Number of complete byte bn[1]
B4 Txl0 Number of complete byte bn[0]
B3 Bb2 Broken byte number of bits bb[2] Number of bits in the last broken byte to be transmitted. This bit is taken into account only when the broken byte flag is set.
B2 Bb1 Broken byte number of bits bb[1]
B1 Bb0 Broken byte number of bits bb[0]
B0 Bbf Broken byte flag If 1, the last byte is not complete and is less than 8 bits wide.

Direct Commands From MCU to Reader

Command Codes

Table 6-31 describes the command codes.

Table 6-31 Command Codes

COMMAND CODE COMMAND COMMENTS
0x00 Idle
0x03 Software Initialization Software initialization, same as power-on reset
0x0F Reset FIFO
0x10 Transmission Without CRC
0x11 Transmission With CRC
0x12 Delayed Transmission Without CRC
0x13 Delayed Transmission With CRC
0x14 Transmit Next Time Slot Used for ISO/IEC 15693 only
0x16 Block Receiver
0x17 Enable Receiver
0x18 Test Internal RF RSSI at RX input with TX on
0x19 Test External RF RSSI at RX input with TX off
0x1A Receiver Gain Adjust

NOTE

The command code values in Table 6-31 are substituted in Table 6-33, bit 0 to bit 4. The MSB in Table 6-33 must be set to 1.

Reset FIFO

The Reset FIFO command clears the FIFO contents and FIFO Status register (1Ch) and the Collision Position register (0Eh).

Transmission With CRC

The transmission command must be sent first, followed by transmission length bytes, and then the FIFO data. The reader starts transmitting after the first byte is loaded into the FIFO. The CRC byte is included in the transmitted sequence.

Transmission Without CRC

Same as Section 6.5.3 with CRC excluded.

Delayed Transmission With CRC

The transmission command must be sent first, followed by the transmission length bytes, and then the FIFO data. The reader transmission is triggered by the TX timer.

Delayed Transmission Without CRC

Same as Section 6.5.5 with CRC excluded.

Transmit Next Time Slot

When this command is received, the reader transmits the next slot command. The next slot sign is defined by the protocol selection. This command is used for ISO/IEC 15693 only.

Receiver Gain Adjust

This command should be executed when the MCU determines that no tag response is coming and when the RF and receivers are on. When this command is received, the reader reads the digitized receiver output. If more than two edges are observed in 100 µs, the window comparator voltage is increased. The procedure is repeated until the number of edges (changes of logical state) of the digitized reception signal is less than 2 (in 100 µs). The command can reduce the input sensitivity in 5-dB increments up to 15 dB. This command ensures better operation in a noisy environment.

The gain setting is reset to maximum gain at EN = 0, POR = 1.

Test External RF (RSSI at RX Input With TX Off)

This command can be used in active mode when the RF receiver is on, and the RF output is off (rec-on, bit B1 = 1 in the Chip Status Control register [see Table 6-11]). The level of the RF signal received on the antenna is measured and reported in the RSSI Levels register. The relation between the 3-bit code and the external RF field strength (in A/m) must be determined by calculation or by experiments for each antenna design. The antenna Q and connection to the RF input influence the result. The nominal relationship between the RF peak-to-peak voltage at the receiver inputs and the corresponding RSSI level is as follows.

Receiver Input (mVPP): 40 60 80 100 140 180 300
RSSI Level: 1 2 3 4 5 6 7

If the direct command Test RF Internal or Test RF External is used immediately after activation, the command should be preceded by the Enable RX command to activate the RX section. For proper execution of the test RF commands, the RX section must be enabled. This section is enabled automatically when a data exchange between the reader and the tag is done, or by sending the Enable RX direct command.

Test Internal RF (RSSI at RX Input With TX On)

This command measures the level of the RF carrier at the receive inputs. Its operating range is 300 mVp to 2.1 Vp with a step size of 300 mV. The two values are displayed in the RSSI Levels register. The command is intended for diagnostic purposes to set the correct RX_IN levels. The optimum RX_IN input level is approximately 1.6 Vp, or an RSSI level of 5 or 6. The nominal relationship between the input RF peak level and the corresponding RSSI code is as follows.

Receiver Input (mVPP): 300 600 900 1200 1500 1800 2100
RSSI Level: 1 2 3 4 5 6 7

Block Receiver

The Block Receiver command puts the digital part of receiver (bit decoder and framer) in reset mode. This is useful in an extremely noisy environment, where the noise level could otherwise cause a constant switching of the subcarrier input of the digital part of the receiver. The receiver (if not in reset) would try to catch an SOF signal, and if the noise pattern matched the SOF pattern, an interrupt would be generated, falsely signaling the start of an RX operation. A constant flow of interrupt requests can be a problem for the external system (MCU), so the external system can stop this by putting the receive decoders in reset mode. The reset mode can be terminated in two ways. The external system can send the Enable Receiver command. The reset mode is also automatically terminated at the end of a TX operation. The receiver can stay in reset after end of TX if the RX Wait Time register (address 0x08) is set. In this case, the receiver is enabled at the end of the wait time following the transmit operation.

Enable Receiver

This command clears the reset mode in the digital part of the receiver if the reset mode was entered by the Block Receiver command.

Reader Communication Interface

Introduction

The communication interface to the reader can be configured as a parallel 8-pin interface with a data clock or as a serial peripheral interface (SPI). These modes are mutually exclusive; only one mode can be used at a time in the application.

When the SPI is selected, the unused I/O_2, I/O_1, and I/O_0 pins must be hardwired according to Table 6-32. At power up, the TRF7960 IC samples the status of these three pins and then enters one of the possible SPI modes (see Table 6-32).

The reader always acts as the slave while the microcontroller (MCU) acts as the master device. The MCU initiates all communications with the reader and is also used to communicate with the higher levels (application layer). The reader has an IRQ pin to prompt the MCU for attention if the reader detects a response from a proximity integrated circuit card (PICC) or a vicinity integrated circuit card (VICC).

Communication is initialized by a start condition, which is expected to be followed by an Address/Command (Adr/Cmd) word. The Adr/Cmd word is 8 bits long (see Table 6-33).

Table 6-32 Pin Assignment in Parallel and Serial Interface Connection or Direct Mode

PIN PARALLEL PARALLEL DIRECT SPI WITH SS SPI WITHOUT SS
DATA_CLK DATA_CLK DATA_CLK DATA_CLK from master DATA_CLK from master
I/O_7 A/D[7] MOSI(1) = data in (reader in) MOSI(1) = data in (reader in)
I/O_6 A/D[6] Direct mode, data out (subcarrier or bit stream) MISO(2) = data out (MCU out) MISO(2) = data out (MCU out)
I/O_5 A/D[5] Direct mode, strobe – bit clock out See (3) See (3)
I/O_4 A/D[4] SS – slave select(4)  –
I/O_3 A/D[3]  –  –  –
I/O_2 A/D[2]  – At VDD At VDD
I/O_1 A/D[1]  – At VDD At VSS
I/O_0 A/D[0]  – At VSS At VSS
IRQ IRQ interrupt IRQ interrupt IRQ interrupt IRQ interrupt
MOSI = master out, slave in
MISO = master in, slave out
IO_5 pin is used only when data is output from the chip (for example, reading 1 byte from the chip). The master must first write the address of the register (8 clocks) and then generate another 8 clocks to read the data. The IO_5 pin goes high during this second 8 clocks. For normal SPI operation, this pin is not used.
The slave-select pin is active low.

Table 6-33 Address/Command Word Bit Distribution

BIT DESCRIPTION BIT FUNCTION ADDRESS COMMAND
Bit 7 Command control bit 1 = Command, 0 = Address 0 1
Bit 6 Read/write 1 = Read, 0 = Write R/W 0
Bit 5 Continuous address mode 1 = Continuous mode R/W 0
Bit 4 Address/command bit 4 Adr 4 Cmd 4
Bit 3 Address/command bit 3 Adr 3 Cmd 3
Bit 2 Address/command bit 2 Adr 2 Cmd 2
Bit 1 Address/command bit 1 Adr 1 Cmd 1
Bit 0 Address/command bit 0 Adr 0 Cmd 0

The MSB (bit 7) determines if the word is to be used as a command or as an address. The ADDRESS and COMMAND columns of Table 6-33 list the function of the separate bits if either address or command is written. Data is expected when the address word is sent. In continuous-address mode (B5  = 1), the first data that follows the address is written to or read from the given address. For each additional data, the address is incremented by 1. Continuous mode can be used to write to a block of control registers in a single stream without changing the address; for example, setup of the predefined standard control registers from the nonvolatile memory of the MCU to the reader. In noncontinuous address mode (simple addressed mode), only one data word is expected after the address.

Address mode is used to write or read the configuration registers or the FIFO. When writing more than 12 bytes to the FIFO, the continuous address mode should be set to 1.

The command mode is used to enter a command resulting in reader action (for example, initialize transmission, enable reader, or turn reader on or off).

The following examples show the expected communication between the MCU and reader.

Continuous address mode
Start Adr x Data(x) Data(x+1) Data(x+2) Data(x+3) Data(x+4) ... Data(x+n) StopCont
Noncontinuous address mode (single address mode)
Start Adr x Data(x) Adr y Data(y) ... Adr z Data(z) StopSgl
Command mode
Start Cmd x (Optional data or command) Stop

Parallel Interface Communication

In parallel mode, the start condition is generated on the rising edge of the I/O_7 pin while the CLK is high. This condition resets the interface logic. Figure 6-6 shows the sequence of the data, with an 8-bit address word followed by data and ending with the StopSmpl condition. Figure 6-7 shows a similar sequence, except that it ends with the StopCont condition.

Communication is ended by:

  • The StopSmpl condition, which is indicated when the falling edge on the I/O_7 pin is detected while CLK is high
  • The StopCont condition, which is indicated when the I/O_7 pin has successive rising and falling edges while CLK is low. This condition resets the parallel interface, and the device is ready for a new communication sequence.

The StopSmpl condition also terminates the direct mode.

TRF7960 TRF7961 stopsmpl_lou186.gif Figure 6-6 Parallel Interface Communication With Simple Stop Condition StopSmpl
TRF7960 TRF7961 stopcont_lou186.gif Figure 6-7 Parallel Interface Communication With Continuous Stop Condition StopCont

Receive

At the start of a receive operation (when SOF is successfully detected), B6 is set in the IRQ Status register. An interrupt request is sent to the MCU at the end of the receive operation if the receive data string was shorter than or equal to 8 bytes. The MCU receives the interrupt request, then checks to determine the reason for the interrupt by reading the IRQ Status register (address 0Ch), after which the MCU reads the data from the FIFO.

If the received packet is longer than 8 bytes, the interrupt is sent before the end of the receive operation when the ninth byte is loaded into the FIFO (75% full). The MCU should again read the content of the IRQ Status register to determine the cause of the interrupt request. If the FIFO is 75% full (as marked with flag B5 in the IRQ Status register and by reading the FIFO Status register), the MCU should respond by reading the data from the FIFO to make room for new incoming receive data. When the receive operation is finished, the interrupt is sent and the MCU must check how many words are still present in the FIFO before it finishes reading.

If the reader detects a receive error, the corresponding error flag is set (for example, framing error or CRC error) in the IRQ Status register, which indicates that the MCU reception was completed incorrectly.

Transmit

Before beginning data transmission (see Figure 6-8), the FIFO should be cleared with a reset command (0x0F). Data transmission is initiated with a selected command (see Table 6-31). The MCU then commands the reader to do a continuous write command (3Dh, see Table 6-33) starting from register 1Dh. Data written into register 1Dh is the TX Length Byte1 (upper and middle nibbles), while the next byte in register 1Eh is the TX Length Byte2 (lower nibble and broken byte length). The TX byte length determines when the reader sends the EOF byte. After the TX Length Bytes are written, FIFO data is loaded in register 1Fh with byte storage locations 0 to 11. Data transmission begins automatically after the first byte is written into the FIFO. The loading of TX Length Bytes and the FIFO can be done with a continuous-write command, because the addresses are sequential.

At the start of transmission, the Irq_tx flag (B7) is set in the IRQ Status register. If the transmit data is shorter than or equal to 4 bytes, the interrupt is sent only at the end of the transmit operation. If the number of bytes to be transmitted is greater than or equal to 5, the interrupt is generated. The interrupt is also generated when the number of bytes in the FIFO reaches 3. The MCU should check the IRQ Status register and the FIFO Status register and then load additional data to the FIFO, if needed. At the end of the transmit operation, an interrupt is sent to notify the MCU that the task is complete.

TRF7960 TRF7961 data_clk_op_lou186.gif Figure 6-8 Data Output Only When CLK Is High

Serial Interface Communication

When a SPI is required, parallel I/O pins I/O_2, I/O_1, and I/O_0, must be hardwired according to Table 6-32. On power up, the reader detects the status of these pins; if they are not the same (not all high, or not all low), the reader enters into one of two possible SPI modes.

The serial communications work in the same manner as the parallel communications with respect to the FIFO, except for the following condition. On receiving an IRQ from the reader, the MCU reads the IRQ Status register of the reader to determine how to service the reader. After this, the MCU must do a dummy read to clear the IRQ Status register of the reader. The dummy read is required in SPI mode, because the IRQ Status register of the reader needs an additional clock cycle to clear the register. This is not required in parallel mode, because the additional clock cycle is included in the stop condition. The recommended clock frequency on the DATA_CLK line is 2 MHz.

A procedure for a dummy read follows:

  1. Start the dummy read:
    1. When using slave select (SS), set the SS bit low.
    2. When not using SS, the start condition occurs when SCLK is high (see Figure 6-9).
  2. Send the address word to the IRQ Status register (0Ch) with read and continuous address mode bits set to 1 (see Table 6-33).
  3. Read 1 byte (8 bits) from the IRQ Status register (0Ch).
  4. Dummy read 1 byte from register 0Dh (collision position and interrupt mask).
  5. Stop the dummy read:
    1. When using slave select (SS), set the SS bit high.
    2. When not using SS, the stop condition occurs when SCLK is high (see Figure 6-9).

SPI Without SS* (Slave Select) Pin

The serial interface without the slave select pin must use delimiters for the start and stop conditions. Between these delimiters, the address, data, and command words can be transferred. All words must be 8 bits long with MSB transmitted first.

TRF7960 TRF7961 spi_iface_lou186.gif Figure 6-9 Serial – SPI Communication (No SS* Pin)

In this mode, a rising edge on Data IN (I/O_7, pin 24) while SCLK is high resets the serial interface and prepares it to receive data. Data IN can change only when SCLK is low and is taken by the reader on the rising edge of SCLK. Communication is terminated by the stop condition when the falling edge of Data IN occurs during a high SCLK period.

SPI With SS* (Slave Select) Pin

The serial interface is in reset while the SS* signal is high. Serial data-in (MOSI) changes on the falling edge, and is validated in the reader on the rising edge, as shown in Figure 6-10. Communication is terminated when the SS* signal goes high.

All words must be 8 bits long with the MSB transmitted first.

TRF7960 TRF7961 serial_write_lou186.gif Figure 6-10 Serial – SPI Communication (Write Mode)

Figure 6-11 shows the SPI read operation.

TRF7960 TRF7961 serial_read_lou186.gif
Figure 6-11 Serial – SPI Communication (Read Mode)

The read command is sent out on the MOSI pin, MSB first, in the first eight clock cycles. MOSI data changes on the falling edge, and is validated in the reader on the rising edge (see Figure 6-11). During the write cycle, the serial data out (MISO) is not valid. After the last read command bit (B0) is validated at the eighth rising edge of SCLK, after half a clock cycle, valid data can be read on the MISO pin at the falling edge of SCLK. It takes eight clock edges to read out the full byte (MSB first).

NOTE

When using the hardware SPI (for example, an MSP430 hardware SPI) to implement this feature, take care to switch the SCLK polarity after the write phase for proper read operation. Figure 6-11 shows the example clock polarity for the MSP430-specific environment in the Write Mode and Read Mode sections. See the SPI chapter of the family user's guide for any specific microcontroller family for further information on the setting the appropriate clock polarity.

This clock polarity switch must be done for all read operations (single or continuous).

The MOSI (serial data out) should not have any transitions (all high or all low) during the read cycle. Also, the SS* signal should be low during the whole write and read operation.

Figure 6-12 shows the continuous read operation.

TRF7960 TRF7961 spi_con_read_lou186.gif Figure 6-12 SPI Communication (Continuous Read Mode)

NOTE

Special steps are needed to read the TRF796x IRQ Status register (register address 0x0C) in SPI mode. The status of the bits in this register are cleared after a dummy read. The following steps must be followed when reading the IRQ Status register.

1. Write command 0x6C: read the IRQ Status register in continuous mode (eight clocks).

2. Read the data in register 0x0C (eight clocks).

3. Generate another eight clocks (as if reading the data in register 0x0D) but ignore the MISO data line.

See Figure 6-13 for an example of this process.

TRF7960 TRF7961 spi_irq_read_lou186.gif Figure 6-13 SPI Communication (IRQ Status Register Read)

FIFO Operation

The FIFO is a 12-byte register at address 0x1F with byte storage locations 0 to 11. FIFO data is loaded in a cyclical manner and can be cleared by a Reset command (0x0F).

Two counters and three FIFO status flags are associated with the FIFO. The first counter is a 4-bit FIFO byte counter (bits B0 to B3 in register 0x1C) that keeps track of the number of bytes loaded into the FIFO. If the number of bytes in the FIFO is n, the register value is (n – 1) number of bytes in FIFO register. For example, if 8 bytes are in the FIFO, the FIFO counter (bits B0 to B3 in register 0x1C) has the value 7.

A second counter (12 bits wide) indicates the number of bytes being transmitted (registers 1Dh and 1Eh) in a data frame. An extension to the transmission-byte counter is a 4-bit broken-byte counter also provided in register 1Eh (bits B0:B3). Together, these counters make up the TX length value that determines when the reader generates the EOF byte.

FIFO status flags are as follows:

  1. FIFO overflow (bit B4 of register 0x1C) – indicates that the FIFO was loaded too soon
  2. FIFO level too low (bit B5 of register 0x1C) – indicates that only 3 bytes are left to be transmitted (Can be used during transmission.)
  3. FIFO level high (bit B6 of register 0x1C) – indicates that 9 bytes are already loaded into the FIFO (Can be used during reception to generate a FIFO reception IRQ. This is to notify the MCU to service the reader in time to ensure a continuous data stream.)

During transmission, the FIFO is checked for an almost-empty condition, and during reception, the FIFO is checked for an almost-full condition. The maximum number of bytes that can be loaded into the FIFO in one sequence is 12 bytes. The number of bytes in a frame, transmitted or received, can be greater than 12 bytes.

During transmission, the MCU loads the reader FIFO (or during reception, the MCU removes data from the FIFO), and the FIFO counter counts the number of bytes being loaded into the FIFO. Meanwhile, the byte counter keeps track of the number of bytes being transmitted. An interrupt request is generated if the number of bytes in the FIFO is less than 3 or greater than 9, so that the MCU can send new data or remove the data as necessary. The MCU also checks the number of data bytes to be sent, so as to not surpass the value defined in TX Length Bytes. The MCU also signals the transmit logic when the last byte of data is sent or was removed from the FIFO during reception. Transmission starts automatically after the first byte is written into the FIFO.