8.3.1 VCO

The TRF3761 integrates a high-performance, LC tank, voltage-controlled oscillator (VCO). For each of the devices of the TRF3761 family, the inductance and capacitance of the tank are optimized to yield the best phase-noise performance. The VCO output is fed externally and to the prescaler through a series of very low noise buffers, that greatly reduce the effect of load pulling onto the VCO.

8.3.2 Divide by 2, by 4, and Output Buffer

To extend the frequency coverage, the TRF3761 integrates a divide by 2 and by 4 with a low noise floor. The VCO signal is fed externally through a final open-collector differential-output buffer. This buffer is able to provide up to 3dBm (typical) of power into a 200Ω differential resistive load. The open-collector structure gives the flexibility to choose different load configurations to meet different requirements.

8.3.3 N-Divider

8.3.3.1 Prescaler Stage

This stage divides down the VCO frequency before the A and B counters. This is a dual-modulus prescaler and the user can select any of the following settings: 8/9, 16/17, 32/33, and 64/65. Prescaling is used due to the fact that the internal devices are limited in frequency operations of 200MHz. To determine the proper prescaler value, Fout which is the frequency out of the VCO is divided by the numerator of the prescaler if the answer is less than 200 MHz then that is the prescalar to use, see Equation 1. If the value is higher than 200 MHz then repeat this procedure with the next prescalar numerator until a value of 200MHz or less is achieved. Refer to Synthesizing a Selected Frequency.

Equation 1.

8.3.3.2 A and B Counter Stage

The TRF3761 includes a 6-bit A counter and a 13-bit B counter that operate on the output of the prescaler. The A counter can take values from 0 to 63, while the B counter can take values from 3 to 8191. Also, the value for the B counter must be greater than or equal to the value for the A counter. The A and B counter with the prescaler stage create the VCO N-divider, see Equation 2 and Equation 3. Refer to Synthesizing a Selected Frequency.

Equation 2.

Equation 3.

8.3.3.3 Reference Divider

TRF3761 includes a 14-bit RDiv, also known as RDiv, that allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD) this clock is also known as F_PFD which is also the channel step size. Division ratios from 1 to 16,383 are allowed. To determine RDiv use Equation 4.

Equation 4.

The output frequency (Fout) is determined using Equation 5.

Equation 5.

8.3.4 Phase Frequency Detector (PFD) and Charge Pump Stage

The outputs of the RDiv and the N counter are fed into the PFD stage, where the two signals are compared in frequency and phase. The TRF3761 features an anti-backlash pulse, whose width is controllable by the user through the serial programming interface. The PFD feeds the charge pump, whose output current pulses are fed into an external loop filter, which eventually produces the tuning voltage needed to control the integrated VCO to the desired frequency.

8.3.5 Mux Out

MUX_OUT pin (39) provides a communication port to the microcontroller circuit. See Table 4 in the Detailed Design Procedure section.

8.3.6 Div 1/2/4

Div 1/2/4 is the frequency divider for the TRF3761. This circuit can be programmed thru the serial programming interface (SPI) to divide the output frequency of the VCO by 1, 2 or 4. This feature allows for the same loop filter design to be used for any of the 3 divide by modes, 1, 2 and 4. For example, if the VCO is running at 1499MHz to 1608MHz band then with the same exact circuit, run the output in the divide by 2 mode 749.5MHz to 804MHz band or in the divide by 4 mode 374.75MHz to 402MHz.

8.3.7 Serial interface

The programming interface pins (3, 4, 5) to the chip are the serial programming interface (SPI). The interface requires a Clock, Data, and Strobe signal to operate. See timing diagram Figure 83.

8.3.8 CHIP ENABLE

This feature provides a way to shut down the chip when not needed in order to conserve power. CHIP_EN Pin (2) needs to be High for normal operation.

8.3.9 Buffer Power Down

PD_OUTBUFF pin (1), when enabled in software can provide a -40dB reduction in the output power while the VCO is locked and running. This feature is to help with isolation between RX and TX.

8.3.10 External VCO IN

EXT_VCO_IN pin (18) allows for the use of an external VCO to use the phase lock loop circuit in the TRF3761. This feature enables higher frequencies to be synthesized.

8.4.1 Programmable Divider Mode

TRF3761 frequency range is extended by integrating a divide by 2 and by 4 options. The VCO signal is fed externally through differential-output buffer. The divider block allows to divide the output frequency of the VCO by 1, 2 or 4 by programming thru serial programming interface (SPI). These 3 divide by modes of 1, 2 and 4 enables the usage of same loop filter for wider frequency coverage.

8.5.1 Serial Interface Programming Registers Definition

The TRF3761 features a 3-wire serial programming interface that controls an internal, 32-bit shift register. There are a total of 3 signals that need to be applied: the CLOCK (pin 3), the serial DATA (pin 4) and the STROBE (pin 5). The DATA (DB0-DB31) is loaded LSB first and is read on the rising edge of the CLOCK. The STROBE is asynchronous to the CLOCK and at its rising edge the data in the shift register gets loaded onto the selected internal register. The first four bits (DB0-DB3) is the address to select the available internal registers.

A. The first 4 bits, DB(3-0), of data are Address bits. The 28 remaining bits, DB(31-4), are part of the command. The command is little endian or lower bits first.

Figure 83. Serial Programming Timing Diagram

8.6.1 Register 1

OUT_MODE<1,0>: TRF3761 has an optional divide by 2 or 4 output, which is selectable by programming bits <OUT_MODE_1, OUT_MODE_0> of register 1 (see Table 1).

CP_TEST: By setting bit DB30 to 1 it is possible to test the PFD up or down pulses. Internal TI use only.

TRIS_CP: If bit DB29 is set to 1, the charge pump output goes in tri-state. For normal operation, DB29 must be set to 0.

ABPW: Bits <DB27, DB26> are used to program the width of the anti-backlash pulses of the PFD. The user selects one of the following values: 0.9ns, 1.5ns, 2.7ns and 3.8ns. Backlash can occur when Fpfd becomes phase aligned with Fout of the VCO. This will cause a high impedance state on the phase detector and allow the output frequency to drift until the phase difference is enough to cause the phase detector to start sending signals to the charge pump to correct the difference. This slight variation will show up as a sub harmonic of the pfd signal in the passband of the loop filter which would result in a significant spur in the output of the VCO. It is recommended that the anti-backlash pulse be set to the 1.5ns which gives the best spur reduction for the TRF3761.

PFD_POL: Bit DB28 of register 1 sets the polarity of the PFD. A Low (0) selects a negative polarity, and a High (1) selects a positive polarity. By choosing the correct polarity, the TRF3761 will works with an external VCO having both positive and negative gain (Kv). For example if an external VCO has a Kv = –23MHz/V then the PFD polarity would need to be negative, so DB28 would be set to a Low (0). When using the internal VCO with a Kv of 23MHz/V, the PDF_POL should be set to 1.

RDiv: A 14-bit word programs the RDiv for the reference signal, DB25 is the MSB and DB12 is the LSB. RDiv value is determined by dividing the reference frequency by the channel step size. For example if the reference frequency is 10MHz and the channel step size is 200KHz then RDiv would be 50. This sets up the Fpfd for the phase detector, in other words the reference frequency will be divided down by a factor of RDiv which in this example is 50.

ICP: Bits <DB7, DB5> set the charge pump current.

Equation 6.

which reduces to:

Equation 7.

where N = decimal value of [Reg1 DB<7:5>]. The range is set by N and Rbias2. It is recommended that Icp be set to 7mA or <DB7, DB5>=101.

OUTBUF_EN_SEL: Output buffer on/off state is controlled through serial interface or an external pin. If bit DB10 is a 0 (default state) the output buffers state is elected through bit DB11. If DB10 is a 1, the buffers on/off are directly controlled by the OUTBU_EN pin.

RESET: Setting bit DB4 to 1, all registers are reset to default values.

Refer to Register 1 under the Detailed Design Procedure section.

8.6.2 Register 2

Reference Frequency: The 14 bits <DB17, DB4> are used to specify the input reference frequency as multiples of 10kHz. Bits <DB10,DB4> specify the integer part of the reference frequency expressed in MHz. Bits <DB17,DB11> set the fraction part. Those values are then used during the calibration of the internal VCO. For example if using a 20MHz reference oscillator then bits<DB10,DB4> would be 0010100 and bits<DB17,DB11> would be 0000000. If the reference oscillator is 13.1MHz then bits<DB10,DB4> would be 0001101 and bits<DB17,DB11> would be 0001010.

Start Calibration: A 1 in DB31 starts the internal VCO calibration. When the calibration is complete, DB31 bit is internally reset to 0.

FOUT<12,0>: This 13-bit word <DB30,DB18> specifies the VCO output frequency in MHz. If output frequency is not a integer multiple of MHz, this value must be approximated to the closest integer in MHz.

Refer to Register 2 under the Detailed Design Procedure section.

8.6.3 Register 3

B<12,0>: This 13-bit word <DB24,DB12> controls the value of the B counter of the N divider. The valid range is from 3 to 8191.

A<5,0>: These 6 bits <DB11,DB6> control the value of the A counter. The valid range is from 0 to 63.

PRESC_MOD<1,0>: These bits <DB5,DB4> define the mode of the dual-modulus prescaler according to Table 3.

START_LK: TRF3761 does not load the serial interface registers values into the dividers registers until bit DB29 of register 3 is set to 1. After TRF3761 is locked to the new frequency, bit DB29 is internally reset to 0.

Refer to Register 3 under the Detailed Design Procedure section.