ZHCSQF3B april   2022  – june 2023 TPSI2140-Q1

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. Pin Configuration and Functions
    1. 5.1 Pin Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Avalanche Robustness
    4. 8.4 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Dielectric Withstand Testing (HiPot)
      2. 9.2.2 Design Requirements
      3. 9.2.3 Design Procedure - Chassis Ground Reference
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 静电放电警告
    5. 10.5 术语表
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Layout Example

Varying PCB implementations are possible depending on both the system EMI requirements and the system dielectric withstand testing (HiPot) parameters. The following sections detail the TPSI2140-Q1 EVM with Thermal Optimization with secondary side metallization for optimized thermal performance and the Interlayer Stitch Capacitance Option for EMI and Thermal Optimization.

TPSI2140-Q1 EVM with Thermal Optimization

The TPSI2140-Q1 EVM images below demonstrate a secondary side thermal metallization pattern and internal floating metal that provides thermal relief to the TPSI2140-Q1 during system dielectric withstand testing (HiPot). The TPSI2140-Q1 Secondary Side Layout Recommendation for Optimized Thermal Performance: Top Layer 1 shows the top side creepage and clearance considerations.

GUID-20230530-SS0I-G2VM-VSNH-R0R80FJ2BGKT-low.svg Figure 9-12 TPSI2140-Q1 EVM - Component View
GUID-20230530-SS0I-2DSD-GTMN-T59ZKK0DGHL8-low.svg Figure 9-13 TPSI2140-Q1 EVM - Layer 1
GUID-20230530-SS0I-LBSM-J5V5-GT5S3JL2KKG5-low.svg Figure 9-14 TPSI2140-Q1 EVM - Layer 2
GUID-20230530-SS0I-LDH9-PQPJ-KW0RSQ5PPMVD-low.svg Figure 9-15 TPSI2140-Q1 EVM - Layer 3
GUID-20230530-SS0I-JM5K-CF2X-8GZZT1KDZH1J-low.svg Figure 9-16 TPSI2140-Q1 EVM - Layer 4
GUID-20221116-SS0I-P5DP-SSFM-FPZNL7VS1KMM-low.svg Figure 9-17 TPSI2140-Q1 Secondary Side Layout Recommendation for Optimized Thermal Performance: Top Layer 1
GUID-20221116-SS0I-ZS71-WV9H-42THTFGVCWCP-low.svg Figure 9-18 TPSI2140-Q1 Secondary Side Layout Recommendation for Optimized Thermal Performance: Inner Layer 2
GUID-20221116-SS0I-3M3P-NCG6-PTG6RGQXXQCP-low.svg Figure 9-19 TPSI2140-Q1 Secondary Side Layout Recommendation for Optimized Thermal Performance: Inner Layer 3
GUID-20221116-SS0I-SVFT-GFF7-JRPNGDXKQBSB-low.svg Figure 9-20 TPSI2140-Q1 Secondary Side Layout Recommendation for Optimized Thermal Performance: Bottom Layer 4

Interlayer Stitch Capacitance Option for EMI and Thermal Optimization

The layout example below demonstrates an EMI optimized and thermally optimized PCB Design for high voltage switching applications. The overlapping metal layers beneath the TPSI2140-Q1 form an interlayer stitching capacitance between the primary side ground and the S2 pin and increase the board copper content, improving the thermal performance for dielectric withstand testing (HiPot). Using S1 or S2 as the secondary side interlayer stitching capacitance terminal is equally effective. Metal islands on the S1 and S2 pin on the top side and inner layers further improve the thermal performance. Care should be taken to maintain both the vertical and horizontal interlayer dielectric (ILD) spacings between high voltage terminals required by the system.

GUID-20230530-SS0I-7HLX-4HWH-W9QCN51K4TRW-low.svg Figure 9-21 TPSI2140-Q1 Layout with Interlayer Stitch Capacitance: Top Layer (1)
GUID-20230530-SS0I-CZ8N-81HN-VT921QKCXHV7-low.svg Figure 9-22 TPSI2140-Q1 Layout with Interlayer Stitch Capacitance: Inner Layer (2,4)
GUID-20230530-SS0I-C5RS-TNLK-VRWP3PJHDS36-low.svg Figure 9-23 TPSI2140-Q1 Layout with Interlayer Stitch Capacitance: Inner Layer (3)