ZHCSGD1 June   2017 TPS82140

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommend Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM and PSM Operation
      2. 7.3.2 Low Dropout Operation (100% Duty Cycle)
      3. 7.3.3 Switch Current Limit
      4. 7.3.4 Undervoltage Lockout
      5. 7.3.5 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable and Disable (EN)
      2. 7.4.2 Soft Startup (SS/TR)
      3. 7.4.3 Voltage Tracking (SS/TR)
      4. 7.4.4 Power Good Output (PG)
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 1.8-V Output Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design with WEBENCH® Tools
          2. 8.2.1.2.2 Setting the Output Voltage
          3. 8.2.1.2.3 Input and Output Capacitor Selection
          4. 8.2.1.2.4 Soft Startup Capacitor Selection
        3. 8.2.1.3 Application Performance Curves
    3. 8.3 System Examples
      1. 8.3.1 Inverting Power Supply
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Consideration
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 开发支持
        1. 11.1.2.1 使用 WEBENCH® 工具定制设计方案
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
  • SIL|8
散热焊盘机械数据 (封装 | 引脚)
订购信息

Detailed Description

Overview

The TPS82140 synchronous step-down converter MicroSiP™ power module is based on DCS-Control™ (Direct Control with Seamless transition into Power Save Mode). This is an advanced regulation topology that combines the advantages of hysteretic and voltage mode control.

The DCS-Control™ topology operates in PWM (Pulse Width Modulation) mode for medium to heavy load conditions and in PSM (Power Save Mode) at light load currents. In PWM mode, the converter operates with its nominal switching frequency of 2.0MHz having a controlled frequency variation over the input voltage range. As the load current decreases, the converter enters Power Save Mode, reducing the switching frequency and minimizing the IC's quiescent current to achieve high efficiency over the entire load current range. DCS-Control™ supports both operation modes using a single building block and therefore has a seamless transition from PWM to PSM without effects on the output voltage. The TPS82140 offers excellent DC voltage regulation and load transient regulation, combined with low output voltage ripple, minimizing interference with RF circuits.

Functional Block Diagram

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TPS82140 TPS82140_fbd.gif

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Feature Description

PWM and PSM Operation

The TPS82140 includes an on-time (tON) circuitry. This tON, in steady-state operation in PWM and PSM modes, is estimated as:

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Equation 1. TPS82140 TPS82130_EQ_ton.gif

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In PWM mode, the TPS82140 operates with pulse width modulation in continuous conduction mode (CCM) with a tON shown in Equation 1 at medium and heavy load currents. A PWM switching frequency of typically 2.0MHz is achieved by this tON circuitry. The device operates in PWM mode as long as the output current is higher than half the inductor's ripple current estimated by Equation 2.

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Equation 2. TPS82140 EQ_ILripple.gif

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To maintain high efficiency at light loads, the device enters Power Save Mode seamlessly when the load current decreases. This happens when the load current becomes smaller than half the inductor's ripple current. In PSM, the converter operates with reduced switching frequency and with a minimum quiescent current to maintain high efficiency. PSM is also based on the tON circuitry. The switching frequency in PSM is estimated as:

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Equation 3. TPS82140 EQ_FSWPSM.gif

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In PSM, the output voltage rises slightly above the nominal output voltage in PWM mode. This effect is reduced by increasing the output capacitance. The output voltage accuracy in PSM operation is reflected in the electrical specification table and given for a 22-µF output capacitor.

For very small output voltages, an absolute minimum on-time of about 80ns is kept to limit switching losses. The operating frequency is thereby reduced from its nominal value, which keeps efficiency high. Also the off-time can reach its minimum value at high duty cycles. The output voltage remains regulated in such cases.

When VIN decreases to typically 15% above VOUT, the TPS82140 can't enter Power Save Mode, regardless of the load current. The device maintains output regulation in PWM mode.

Low Dropout Operation (100% Duty Cycle)

The TPS82140 offers a low input to output voltage differential by entering 100% duty cycle mode. In this mode, the high-side MOSFET switch is constantly turned on. This is particularly useful in battery powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage to maintain a minimum output voltage is given by:

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Equation 4. TPS82140 TPS82130_EQ_dropout.gif

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Where

RDP = Resistance from VIN to VOUT, including high-side FET on-resistance and DC resistance of the inductor

VOUT(min) = Minimum output voltage the load can accept.

Switch Current Limit

The switch current limit prevents the device from high inductor current and from drawing excessive current from the battery or input voltage rail. Excessive current might occur with a heavy load/shorted output circuit condition. If the inductor peak current reaches the switch current limit after a propagation delay of typically 30ns, the high-side FET is turned off and the low-side FET is turned on to ramp down the inductor current.

Undervoltage Lockout

To avoid mis-operation of the device at low input voltages, an under voltage lockout is implemented, which shuts down the devices at voltages lower than VUVLO with a hysteresis of 200mV.

Thermal Shutdown

The device goes into thermal shutdown and stops switching once the junction temperature exceeds TJSD. Once the device temperature falls below the threshold by 20°C, the device returns to normal operation automatically.

Device Functional Modes

Enable and Disable (EN)

The device is enabled by setting the EN pin to a logic High. Accordingly, the shutdown mode is forced if the EN pin is pulled Low with a shutdown current of typically 1.5 μA.

An internal pull-down resistor of 400kΩ is connected to the EN pin when the EN pin is Low. The pull-down resistor is disconnected when the EN pin is High.

Soft Startup (SS/TR)

The internal voltage clamp controls the output voltage slope during startup. This avoids excessive inrush current and ensures a controlled output voltage rise time. When the EN pin is pulled high, the device starts switching after a delay of typically 55μs and the output voltage rises with a slope controlled by an external capacitor connected to the SS/TR pin. Using a very small capacitor or leaving the SS/TR pin floating provides fastest startup time.

The TPS82140 is able to start into a pre-biased output capacitor. During the pre-biased startup, both the power MOSFETs are not allowed to turn on until the internal voltage clamp sets an output voltage above the pre-bias voltage.

When the device is in shutdown, undervoltage lockout or thermal shutdown, the capacitor connected to SS/TR pin is discharged by an internal resistor. Returning from those states causes a new startup sequence.

Voltage Tracking (SS/TR)

The SS/TR pin is externally driven by another voltage source to achieve output voltage tracking. The application circuit is shown in Figure 4.

TPS82140 TPS82140_Voltagetracking.gif Figure 4. Output Voltage Tracking

When the SS/TR pin voltage is between 50 mV and 1.2 V, the VOUT2 tracks the VOUT1 as described in Equation 5.

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Equation 5. TPS82140 EQ_Voltagetracking.gif

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When the SS/TR pin voltage is above 1.2 V, the voltage tracking is disabled and the FB pin voltage is regulated at 0.8 V. For decreasing SS/TR pin voltage, the device doesn't sink current from the output. So the resulting decreases of the output voltage may be slower than the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not exceed the voltage rating of the SS/TR pin which is VIN+0.3V.

Details about tracking and sequencing circuits are found in SLVA470.

Power Good Output (PG)

The device has a power good (PG) output. The PG pin goes high impedance once the output is above 95% of the nominal voltage, and is driven low once the output voltage falls below typically 90% of the nominal voltage. The PG pin is an open drain output and is specified to sink up to 2mA. The power good output requires a pull-up resistor connecting to any voltage rail less than 6V.

The PG pin goes low when the device is in shutdown or thermal shutdown. When the device is in UVLO, the PG pin is high impedance. The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin of other converters. Leave the PG pin floating when it is not used. Table 1 shows the PG pin logic.

Table 1. Power Good Pin Logic

Device State PG Logic Status
High Impedance Low
Enable (EN=High) VFB ≥ VTH_PG
VFB ≤ VTH_PG
Shutdown (EN=Low)
UVLO 0.7 V < VIN < VUVLO
Thermal Shutdown TJ > TSD
Power Supply Removal VIN < 0.7 V