ZHCSG47D February   2017  – June 2025 TPS7B63-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Enable (EN)
      2. 6.3.2 Adjustable Power-Good Threshold (PG, PGADJ)
      3. 6.3.3 Adjustable Power-Good Delay Timer (DELAY)
      4. 6.3.4 Undervoltage Shutdown
      5. 6.3.5 Current Limit
      6. 6.3.6 Thermal Shutdown
      7. 6.3.7 Integrated Watchdog
        1. 6.3.7.1 Window Watchdog (WTS, ROSC, FSEL and WRS)
        2. 6.3.7.2 Standard Watchdog (WTS, ROSC and FSEL)
        3. 6.3.7.3 Watchdog Service Signal and Watchdog Fault Outputs (WD and WDO)
        4. 6.3.7.4 ROSC Status Detection (ROSC)
        5. 6.3.7.5 Watchdog Enable (PG and WD_EN)
        6. 6.3.7.6 Watchdog Initialization
        7. 6.3.7.7 Window Watchdog Operation (WTS = Low)
        8. 6.3.7.8 Standard Watchdog Operation (WTS = High)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Operation With Input Voltage Lower Than 4 V
      2. 6.4.2 Operation With Input Voltage Higher Than 4 V
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input Capacitor
        2. 7.2.2.2 Output Capacitor
        3. 7.2.2.3 Power-Good Threshold
        4. 7.2.2.4 Power-Good Delay Period
        5. 7.2.2.5 Watchdog Setup
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 器件和文档支持
    1. 8.1 文档支持
      1. 8.1.1 相关文档
    2. 8.2 接收文档更新通知
    3. 8.3 支持资源
    4. 8.4 商标
    5. 8.5 静电放电警告
    6. 8.6 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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6.3.3 Adjustable Power-Good Delay Timer (DELAY)

The power-good delay period is a function of the value set by an external capacitor on the DELAY pin before turning the PG pin high. Figure 6-2 illustrates typical power-good and delay behavior. Connecting an external capacitor from this pin to GND sets the power-good delay period. The constant current charges an external capacitor until the voltage exceeds a threshold to trip an internal comparator, and Equation 2 determines the power-good delay period:

Equation 2. TPS7B63-Q1

where

  • t(DLY) is the adjustable power-good delay period
  • CDELAY is the value of the power-good delay capacitor
TPS7B63-Q1 Power Up and Conditions for Activating Power-Good Figure 6-2 Power Up and Conditions for Activating Power-Good

If the DELAY pin is open, the default delay time is t(DLY_FIX).