ZHCSI98E November   2010  – March 2020 TPS7A6201-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      典型稳压器稳定性
      2.      应用原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Up
      2. 7.3.2 Adjustable Output Voltage
      3. 7.3.3 Enable Input
      4. 7.3.4 Charge Pump Operation
      5. 7.3.5 Undervoltage Shutdown
      6. 7.3.6 Low Voltage Tracking
      7. 7.3.7 Integrated Fault Protection
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Power Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor
        2. 8.2.2.2 Output Capacitor
        3. 8.2.2.3 Feedback Resistor
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Dissipation and Thermal Considerations
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • KTT|5
散热焊盘机械数据 (封装 | 引脚)
订购信息

10.1.1 Power Dissipation and Thermal Considerations

Calculate the power dissipated in the device using Equation 3.

Equation 3. PD = IOUT × (VIN – VOUT)) + IQUIESCENT × VIN

where

  • PD = continuous power dissipation
  • IOUT = output current
  • VIN = input voltage
  • VOUT = output voltage
  • IQUIESCENT = quiescent current

As IQUIESCENT << IOUT, therefore, the term IQUIESCENT × VIN in Equation 3 can be ignored.

For device under operation at a given ambient air temperature (TA), calculate the junction temperature (TJ) Equation 4.

Equation 4. TJ = TA + (RθJA × PD)

where

  • RθJA = junction to ambient air thermal impedance

Calculate the rise in junction temperature due to power dissipation using Equation 5.

Equation 5. ΔT = TJ – TA = (RθJA × PD)

For a given maximum junction temperature (TJ-Max), calculate the maximum ambient air temperature (TA-Max) at which the device can operate using Equation 6.

Equation 6. TA-Max = TJ-Max – (RθJA × PD)

Example

If IOUT = 100 mA, VOUT = 5 V, VIN = 14 V, IQUIESCENT = 250 µA, and RθJA = 30˚C/W, the continuous power dissipated in the device is 0.9 W. The rise in junction temperature due to power dissipation is 27˚C. For a maximum junction temperature of 150˚C, maximum ambient air temperature at which the device can operate is 123˚C.

For adequate heat dissipation, TI recommends soldering the thermal pad (exposed heat sink) to thermal land pad on the PCB. Doing this provides a heat conduction path from die to the PCB and reduces overall package thermal resistance. Figure 22 illustrates the power derating curves for the TPS7A6201-Q1 device in the KTT (TO-263) package..

TPS7A6201-Q1 power_derating_lvsaa0.gifFigure 22. Power Derating Curves

For optimum thermal performance, TI recommends using a high-K PCB with thermal vias between ground plane and solder pad or thermal land pad. This is shown in Figure 23 (a) and (b). Furthermore, heat spreading capabilities of a PCB can be considerably improved by using a thicker ground plane and a thermal land pad with a larger surface area.

TPS7A6201-Q1 multilayer_pcb_thermal_vias_lvsa62.gifFigure 23. Using Multilayer PCB and Thermal Vias for Adequate Heat Dissipation

Keeping other factors constant, surface area of the thermal land pad contributes to heat dissipation only to a certain extent. Figure 24 shows a variation of RθJA with surface area of the thermal land pad (soldered to the exposed pad) for KTT package.

TPS7A6201-Q1 thetaja_vs_thermal_pad_area_lvsaa0.gifFigure 24. RθJA vs Thermal Pad Area