ZHCS992F June   2012  – September 2014


  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit (ICL)
      2. 7.3.2 Enable (EN) And Under-Voltage Lockout (UVLO)
      3. 7.3.3 Soft-Start And Inrush Current
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 ANY-OUT Programmable Output Voltage
      2. 7.5.2 Adjustable Operation (TPS7A4701 Only)
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Capacitor Recommendations
          1. Input and Output Capacitor Requirements
          2. Noise Reduction Capacitor (CNR)
        2. Dropout Voltage (VDO)
        3. Output Voltage Accuracy
        4. Startup
        5. AC Performance
          1. Power-Supply Rejection Ratio (PSRR)
          2. Load Step Transient Response
          3. Noise
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Power Dissipation (PD)
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Protection
    4. 10.4 Estimating Junction Temperature
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档 
    2. 11.2 相关链接
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 术语表
  12. 12机械封装和可订购信息


机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

10 Layout

10.1 Layout Guidelines

For best overall performance, all circuit components are recommended to be located on the same side of the circuit board and as near as practical to the respective LDO pin connections. Ground return connections to the input and output capacitor, and to the LDO ground pin, must also be as close to each other as possible and connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics and thereby reduces load-current transients, minimizes noise, and increases circuit stability.

A ground reference plane is also recommended. This reference plane serves to assure accuracy of the output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device when connected to the PowerPAD™. In most applications, this ground plane is necessary to meet thermal requirements.

Use the TPS7A4701 evaluation module (EVM), available for purchase from the TI eStore, as a reference for layout and application design.

10.2 Layout Example

layout_sbvs204.gifFigure 28. Layout Example

10.3 Thermal Protection

The TPS7A470x contains a thermal shutdown protection circuit to turn off the output current when excessive heat is dissipated in the LDO. Thermal shutdown occurs when the thermal junction temperature (TJ) of the main pass-FET exceeds 170°C (typical). Thermal shutdown hysteresis assures that the LDO again resets (turns on) when the temperature falls to 150°C (typical). Because the TPS7A470x is capable of supporting high input voltages, a great deal of power can be expected to be dissipated across the device at low output voltages, which causes a thermal shutdown. The thermal time-constant of the semiconductor die is fairly short, and thus the output oscillates on and off at a high rate when thermal shutdown is reached until power dissipation is reduced.

For reliable operation, the junction temperature must be limited to a maximum of 125°C. To estimate the thermal margin in a given layout, increase the ambient temperature until the thermal protection shutdown is triggered using worst-case load and highest input voltage conditions. For good reliability, thermal shutdown must be designed to occur at least 45°C above the maximum expected ambient temperature condition for the application. This configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.

The internal protection circuitry of the TPS7A470x is designed to protect against thermal overload conditions. The circuitry is not intended to replace proper heat sinking. Continuously running the TPS7A470x into thermal shutdown degrades device reliability.

10.4 Estimating Junction Temperature

JEDEC standards now recommend the use of PSI thermal metrics to estimate the junction temperatures of the LDO while in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal resistances, but rather offer practical and relative means of estimating junction temperatures. These PSI metrics are determined to be significantly independent of copper-spreading area. The key thermal metrics (ΨJT and ΨJB) are given in the Thermal Information table and are used in accordance with Equation 9.

Equation 9. q_wjt-wjb_bvs204.gif