具有反向电流保护功能的 TPS737-Q1 1A 低压降稳压器
- ZHCSKA4B December 2008 – September 2019 TPS737-Q1
  
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具有反向电流保护功能的 TPS737-Q1 1A 低压降稳压器

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

符合汽车类应用要求
具有符合 AEC-Q100 标准的下列特性：
- 器件温度等级 1：–40°C 至 125°C 环境工作温度范围
- 器件 HBM ESD 分类等级 2
- 器件 CDM ESD 分类等级 C4A
与 1µF 或更大的陶瓷输出电容器一起工作时保持稳定
输入电压范围：2.2V 至 5.5V
超低压降：1A 为 130mV（典型值）
即使使用仅为 1µF 的输出电容器，也能实现出色的负载瞬态响应
NMOS 拓扑可提供低反向漏电流
初始精度为 1%
整个线路、负载和温度范围内的精度达 3%
关断模式下静态电流小于 20nA（典型值）
通过热关断和电流限制实现故障保护
提供了多个输出电压版本

2 应用

适用于 DSP、FPGA、ASIC 和微处理器的负载点调节
适用于开关电源的后置稳压
便携式和电池供电类设备

3 说明

TPS737xx-Q1 线性低压降 (LDO) 稳压器系列在电压跟随器配置中使用了 NMOS 旁路元件。该拓扑结构对输出电容值和等效串联电阻 (ESR) 的敏感度相对较低，从而实现多种负载配置。即使使用 1µF 的小型陶瓷输出电容器，也能实现出色的负载瞬态响应。NMOS 拓扑结构也可实现极低压降。

TPS737xx-Q1 系列利用先进的 BiCMOS 工艺实现高精度，同时提供极低的压降和低接地引脚电流。未启用时的电流消耗低于 20nA，适用于便携式应用。这些器件受到热关断和折返电流限制的保护。

器件信息⁽¹⁾

器件型号	封装	封装尺寸（标称值）
TPS737-Q1	VSON (8)	3.00mm × 3.00mm

要了解所有可用封装，请参阅数据表末尾的可订购产品附录。

Device Images

典型应用电路

4 修订历史记录

Changes from A Revision (July 2016) to B Revision

Changed 更改了器件温度等级、AEC-Q100 “特性” 项目符号Go
Deleted 删除了子项目符号（从“特性” 输出电压版本 项目符号中）Go

Changes from * Revision (December 2008) to A Revision

Added 添加了器件信息 表、引脚配置和功能 部分、规格部分、ESD 额定值 表、建议运行条件 表、热性能信息 表、详细说明 部分、应用和实施 部分、电源建议 部分、布局部分、器件和文档支持 部分以及机械、封装和可订购信息 部分Go
Deleted 删除了订购信息表，请参阅数据表末尾的 POAGo

5 Pin Configuration and Functions

DRB Package

8-Pin VSON

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
EN	5	I	Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. See Enable Pin and Shutdown for more details. EN must not be left floating and can be connected to IN if not used.
FB	3	I	Adjustable voltage version only. This is the input to the control loop error amplifier, and it is used to set the output voltage of the device.
GND	4, Pad	G	Ground
IN	8	I	Unregulated input supply
NR	3	—	Fixed voltage versions only. Connecting an external capacitor to this pin bypasses noise generated by the internal bandgap, reducing output noise to very low levels.
OUT	1	O	Regulator output. A 1-µF or larger capacitor of any type is required for stability.
NC	2, 6, 7	—	No internal connection

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Input supply voltage		–0.3	6	V
Enable voltage		–0.3	6	V
Output voltage		–0.3	5.5	V
Input voltage	NR or FB pin	–0.3	6	V
Peak output current		Internally limited
Output short-circuit duration		Indefinite
Junction temperature range, T_J		–55	150	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011	±500	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_IN	Input supply voltage	2.2	5.5	V
I_OUT	Output current	0	1	A
T_J	Operating junction temperature	–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS737xx-Q1	UNIT
		DRB (VSON)
		8 PINS
R_θJA	Junction-to-ambient thermal resistance	52.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	59.4	°C/W
R_θJB	Junction-to-board thermal resistance	19.3	°C/W
ψ_JT	Junction-to-top characterization parameter	2	°C/W
ψ_JB	Junction-to-board characterization parameter	19.3	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	11.8	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over operating temperature range (T_J = –40°C to 125°C), V_IN = ( V_OUT(nom) + 1 V )⁽¹⁾, I_OUT = 10 mA, V_EN = 2.2 V, C_OUT = 2.2 µF (unless otherwise noted). Typical values are at T_J = 25°C.

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IN	Input voltage range⁽¹⁾⁽²⁾			2.2		5.5	V
V_FB	Internal reference (TPS73701)		T_J = 25°C	1.192	1.2	1.216	V
V_OUT	Output voltage range (TPS73701)⁽³⁾			V_FB		5.5 – V_DO	V
	Accuracy⁽¹⁾⁽⁴⁾	Nominal	T_J = 25°C	–1		1	%
			5.36 V < V_IN < 5.5 V, V_OUT = 5.08 V, 10 mA < I_OUT < 800 mA, –40°C < T_J < 85°C, TPS73701	–2		2
		Over V_IN, I_OUT, and temperature	V_OUT + 0.5 V ≤ V_IN ≤ 5.5 V, 10 mA ≤ I_OUT ≤ 1 A	–3	±0.5	3
ΔV_OUT% / ΔV_IN	Line regulation⁽¹⁾		V_OUT(nom) + 0.5 V ≤ V_IN ≤ 5.5 V		0.01		%/V
ΔV_OUT% / ΔI_OUT	Load regulation		1 mA ≤ I_OUT ≤ 1 A		0.002		%/mA
ΔV_OUT% / ΔI_OUT	Load regulation		10 mA ≤ I_OUT ≤ 1 A		0.0005		%/mA
V_DO	Dropout voltage⁽⁵⁾ (V_IN = V_OUT(nom) – 0.1 V)		I_OUT = 1 A		130	500	mV
Z_O(DO)	Output impedance in dropout		2.2 V ≤ V_IN ≤ V_OUT + V_DO		0.25		Ω
I_CL	Output current limit		V_OUT = 0.9 × V_OUT(nom)	1.05	1.6	2.2	A
I_SC	Short-circuit current		V_OUT = 0 V		450		mA
I_REV	Reverse leakage current⁽⁶⁾(–I_IN)		V_EN ≤ 0.5 V, 0 V ≤ V_IN ≤ V_OUT		0.1		µA
I_GND	GND pin current		I_OUT = 10 mA (I_Q)		400		µA
I_GND	GND pin current		I_OUT = 1 A		1300		µA
I_SHDN	Shutdown current (I_GND)		V_EN ≤ 0.5 V, V_OUT ≤ V_IN ≤ 5.5 V		20		nA
I_FB	FB pin current (TPS73701)				0.1	0.6	µA
PSRR	Power-supply rejection ratio (ripple rejection)		f = 100 Hz, I_OUT = 1 A		58		dB
PSRR	Power-supply rejection ratio (ripple rejection)		f = 10 kHz, I_OUT = 1 A		37		dB
V_N	Output noise voltage BW = 10 Hz to 100 kHz		C_OUT = 10 µF		27 × V_OUT		µV_RMS
t_STR	Startup time		V_OUT = 3 V, R_L = 30 Ω, C_OUT = 1 µF		600		µs
V_EN(HI)	EN pin high (enabled)			1.7		V_IN	V
V_EN(LO)	EN pin low (shutdown)			0		0.5	V
I_EN(HI)	EN pin current (enabled)		V_EN = 5.5 V		20		nA
T_SD	Thermal shutdown temperature		Shutdown, temperature increasing		160		°C
T_SD	Thermal shutdown temperature		Reset, temperature decreasing		140		°C
T_J	Operating junction temperature			–40		125	°C

(1) Minimum V_IN = V_OUT + V_DO or 2.2 V, whichever is greater.

(2) For V_OUT(nom) < 1.6 V, when V_IN ≤ 1.6 V, the output locks to V_IN and may result in an overvoltage condition on the output. To avoid this situation, disable the device before powering down V_IN.

(3) TPS73701 is tested at V_OUT = 1.2 V.

(4) Tolerance of external resistors not included in this specification.

(5) V_DO is not measured for fixed output versions with V_OUT(nom) < 2.3 V, because minimum V_IN = 2.2 V.

(6) Fixed-voltage versions only; see the Reverse Current section for more information.

6.6 Typical Characteristics

T_J = 25°C, V_IN = ( V_OUT(nom) + 1 V ), I_OUT = 10 mA, V_EN = 2.2 V, C_OUT = 2.2 µF (unless otherwise noted)

Figure 1. Load Regulation

Figure 3. Dropout Voltage vs Output Current

Figure 5. Output Voltage Histogram

Figure 7. Ground Pin Current vs Output Current

TPS737-Q1 tc_ignd_shutdown_tmp_bvs123.gif

Figure 9. Ground Pin Current In Shutdown vs Temperature

Figure 11. Current Limit vs V_IN

Figure 13. PSRR (Ripple Rejection) vs Frequency

Figure 15. Noise Spectral Density

TPS737-Q1 tc_rms_cout_tps736_copy_bvs123.gif

Figure 17. RMS Noise Voltage vs C_OUT

Figure 19. TPS73733 Load Transient Response

Figure 21. TPS73701 Turn-On Response

Figure 23. TPS73701, V_OUT = 3.3 V
Power-Up And Power-Down

Figure 25. TPS73701 I_FB vs Temperature

Figure 27. TPS73701 Load Transient, Adjustable Version

Figure 2. Line Regulation

Figure 4. Dropout Voltage vs Temperature

Figure 6. Dropout Voltage Drift Histogram

Figure 8. Ground Pin Current vs Temperature

Figure 10. Current Limit vs V_OUT (Foldback)

Figure 12. Current Limit vs Temperature

Figure 14. PSRR (Ripple Rejection) vs V_IN – V_OUT

Figure 16. TPS73701 RMS Noise Voltage vs C_FB

TPS737-Q1 tc_rms_cnr_tps736_copy_bvs123.gif

Figure 18. RMS Noise Voltage vs C_NR

Figure 20. TPS73733 Line Transient Response

Figure 22. TPS73701 Turn-Off Response

Figure 24. I_ENABLE vs Temperature

Figure 26. TPS73701 I_FB vs Temperature

Figure 28. TPS73701 Line Transient, Adjustable Version

7 Detailed Description

7.1 Overview

The TPS737xx-Q1 belongs to a family of new generation LDO regulators that use an NMOS pass transistor to achieve ultra-low-dropout performance, reverse current blockage, and freedom from output capacitor constraints. These features combined with an enable input make the TPS737xx-Q1 ideal for portable applications. This regulator family offers a wide selection of fixed output voltage versions and an adjustable output version. All versions have thermal and over-current protection, including foldback current limit.

Table 1. Standard 1% Resistor Values for Common Output Voltages

V_OUT	R₁	R₂
1.2 V	Short	Open
1.5 V	23.2 kΩ	95.3 kΩ
1.8 V	28.kΩ	56.2 kΩ
2.5 V	39.2 kΩ	36.5 kΩ
2.8 V	44.2 kΩ	33.2 kΩ
3 V	46.4 kΩ	33.2 kΩ
3.3 V	52.3 kΩ	30.1 kΩ

7.2 Functional Block Diagrams

Figure 29. Fixed Voltage Version

See Table 1 for standard resistor values.

Figure 30. Adjustable Voltage Version

7.3 Feature Description

7.3.1 Output Noise

A precision bandgap reference is used to generate the internal reference voltage (V_REF). This reference is the dominant noise source within the TPS737xx-Q1 and it generates approximately 32 µV_RMS (10 Hz to 100 kHz) at the reference output (NR). The regulator control loop adds gain to the reference noise with the same gain as the reference voltage, so that the noise voltage of the regulator is approximately given by Equation 1.

Equation 1. TPS737-Q1 q_vn_32_bvs123.gif

Because the value of V_REF is 1.2 V, this relationship reduces to:

Equation 2. TPS737-Q1 q_vn_27_bvs123.gif

for the case of no C_NR.

An internal 27-kΩ resistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltage reference when an external noise reduction capacitor (C_NR) is connected from NR to ground. The total noise in the 10-Hz to 100-kHz bandwidth is reduced by a factor of approximately 3.2 for C_NR = 10 nF, giving the approximate relationship for C_NR = 10 nF in Equation 3.

Equation 3. TPS737-Q1 q_vn_8_5vrm_bvs123.gif

This noise reduction effect is shown in Figure 18.

The TPS737xx-Q1 uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of the NMOS pass element above V_OUT. The charge pump generates approximately 250 µV of switching noise at approximately 4 MHz, however, charge-pump noise contribution is negligible at the output of the regulator for most values of I_OUT and C_OUT.

7.3.2 Internal Current Limit

The TPS737xx-Q1 internal current limit helps protect the regulator during fault conditions. Foldback current limit helps to protect the regulator from damage during output short-circuit conditions by reducing current limit when V_OUT drops below 0.5 V. See Figure 10.