ZHCSEN1A February   2016  – October 2016 TPS720-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Inrush Current Limit
      3. 7.3.3 Shutdown
      4. 7.3.4 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input and Output Capacitor Requirements
      2. 8.1.2 Output Regulation With the IN Pin Floating
      3. 8.1.3 Dropout Voltage
      4. 8.1.4 Transient Response
      5. 8.1.5 Minimum Load
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedures
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
    4. 10.4 Power Dissipation
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
        1. 11.1.1.1 评估模块
      2. 11.1.2 器件命名规则
    2. 11.2 文档支持
      1. 11.2.1 相关文档　
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

DRV Package
6-Pin WSON With Exposed Thermal Pad
Top View
TPS720-Q1 po_drv_bvs100.gif
1. TI recommends connecting the WSON (DRV) package thermal pad to ground.

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
OUT 1 O Output pin. A 2.2-μF ceramic capacitor is connected from this pin to ground for stability and to provide load transients; see Input and Output Capacitor Requirements
NC 2 — No connection.
EN 3 I Enable pin. A logic high signal on this pin turns the device on and regulates the voltage from IN to OUT.
A logic low on this pin turns the device off.
BIAS 4 I Bias supply pin. For better transient performance, TI recommends bypassing this input with a ceramic capacitor to ground; see Input and Output Capacitor Requirements
GND 5 — Ground pin.
IN 6 I Input pin. This pin can be a maximum of 4.5 V; VIN must not exceed VBIAS. Bypass this input with a ceramic capacitor to ground; see Input and Output Capacitor Requirements.