SWCS128A March 2015 – December 2015
PRODUCTION DATA.
MIN | MAX | UNIT | ||
---|---|---|---|---|
ANALOG | ||||
VSYS | Input voltage from battery | –0.3 | 28 | V |
PVIN3, PVIN4, PVIN5, LDO5P0, DRV5V_1_6, DRV5V_2_A1, DRVL1, DRVL2, DRVL6 | –0.3 | 7 | V | |
V5ANA | –0.3 | 6 | V | |
PGNDSNS1, PGNDSNS2, PGNDSNS6, AGND, FBGND2 | –0.3 | 0.3 | V | |
DRVH1, DRVH2, DRVH6, BOOT1, BOOT2, BOOT6 | –0.3 | 34 | V | |
SW1, SW2, SW6 | –2(2) | 28 | V | |
LX3, LX4, LX5 | –1(3) | 7 | V | |
BOOTx to SWx | Differential voltage | –0.3 | 5.5 | V |
VREF, LDO3P3, FBVOUT1, FBVOUT2, FBVOUT6, FB3, FB4, FB5, ILIM1, ILIM2, ILIM6, PVINVTT, VTT, VTTFB, PVINSWA1, SWA1, PVINSWB1_B2, SWB1, SWB2, LDOA1 | –0.3 | 3.6 | V | |
PVINLDOA2_A3, LDOA2, LDOA3 | –0.3 | 3.3 | V | |
DIGITAL IOs | ||||
DATA, CLK, GPO1-GPO3 | –0.3 | 3.6 | V | |
CTL1-CTL6, GPO4, IRQB | –0.3 | 7 | V | |
Tstg | Storage temperature | –40 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
VESD | Electrostatic discharge (ESD) performance | Human Body Model (HBM), per ANSI/ESDA/JEDEC JS001(1) |
±1000 | V | |
Charged Device Model (CDM), per JESD22-C101(2) |
All pins | ±250 | V |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
ANALOG | |||||
VSYS | 5.6 | 13 | 21 | V | |
VREF | –0.3 | 1.3 | V | ||
PVIN3, PVIN4, PVIN5, LDO5P0, V5ANA, DRV5V_1_6, DRV5V_2_A1 | –0.3 | 5 | 5.5 | V | |
PGNDSNS1, PGNDSNS2, PGNDSNS6, AGND, FBGND2 | –0.3 | 0.3 | V | ||
DRVH1, DRVH2, DRVH6, BOOT1, BOOT2, BOOT6 | –0.3 | 26.5 | v | ||
DRVL1, DRVL2, DRVL6 | –0.3 | 5.5 | V | ||
SW1, SW2, SW6 | –1 | 21 | V | ||
LX3, LX4, LX5 | –1 | 5.5 | V | ||
FBVOUT1, FBVOUT2, FBVOUT6, FB3, FB4, FB5 | –0.3 | 3.6 | V | ||
LDO3P3, ILIM1, ILIM2, ILIM6, LDOA1 | –0.3 | 3.3 | V | ||
PVINVTT | –0.3 | 1.2 / 1.35 | FBVOUT6 | V | |
VTT, VTTFB | –0.3 | FBVOUT6 / 2 | V | ||
PVINSWA1, SWA1 | –0.3 | 3.3 | 3.6 | V | |
PVINSWB1_B2, PVINLDOA2_A3, SWB1, SWB2 | –0.3 | 1.8 | V | ||
LDOA2, LDOA3 | –0.3 | 1.5 | V | ||
DIGITAL IOs | |||||
DATA, CLK, CTL1–CTL6, GPO1–GPO4, IRQB | –0.3 | 3.3 | V | ||
CHIP | |||||
TA | Operating ambient temperature range | –40 | 27 | 85 | °C |
TJ | Operating junction temperature range | –40 | 27 | 125 | °C |
THERMAL METRIC(1) | TPS650860 | UNIT | |
---|---|---|---|
RSK (VQFN) | |||
64 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 25.8 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 11.3 | °C/W |
RθJB | Junction-to-board thermal resistance | 4.4 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 4.4 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 0.7 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ISD | PMIC shutdown current that includes IQ for References, LDO5, LDO3P3, and digital core | VSYS = 13 V, all functional output rails are disabled | 65 | µA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
REFERENCE | ||||||
VREF | Bandgap reference Voltage | 1.25 | V | |||
Accuracy | –0.5% | 0.5% | ||||
CVREF | Bandgap output capacitor | 0.047 | 0.1 | 0.22 | µF | |
VSYS_UVLO_5V | VSYS UVLO threshold for LDO5 | VSYS falling | 5.24 | 5.4 | 5.56 | V |
VSYS_UVLO_5V_HYS | VSYS UVLO threshold hysteresis for LDO5 | VSYS rising above VSYS_UVLO_5V |
200 | mV | ||
VSYS_UVLO_3V | VSYS UVLO threshold for LDO3P3 | VSYS falling | 3.45 | 3.6 | 3.75 | V |
VSYS_UVLO_3V_HYS | VSYS UVLO threshold hysteresis for LDO3P3 | VSYS rising above VSYS_UVLO_3V |
150 | mV | ||
TCRIT | Critical threshold of die temperature | TJ rising | 130 | 145 | 160 | °C |
TCRIT_HYS | Hysteresis of TCRIT | TJ falling | 10 | °C | ||
THOT | Hot threshold of die temperature | TJ rising | 110 | 115 | 120 | °C |
THOT_HYS | Hysteresis of THOT | TJ falling | 10 | °C | ||
LDO5 | ||||||
VIN | Input voltage at VSYS pin | 5.6 | 13 | 21 | V | |
VOUT | DC output voltage | IOUT = 10 mA | 4.9 | 5 | 5.1 | V |
IOUT | DC output current | 100 | 180 | mA | ||
IOCP | Overcurrent protection | Measured with output shorted to ground | 200 | mA | ||
VTH_PG | Power Good assertion threshold in percentage of target VOUT | VOUT rising | 94% | |||
VTH_PG_HYS | Power Good deassertion hysteresis | VOUT rising or falling | 4% | |||
IQ | Quiescent current | VIN = 13 V, IOUT = 0 A | 20 | µA | ||
COUT | External output capacitance | 2.7 | 4.7 | 10 | µF | |
V5ANA-to-LDO5P0 LOAD SWITCH | ||||||
RDSON | On resistance | VIN = 5 V, measured from V5ANA pin to LDO5P0 pin at IOUT = 200 mA | 1 | Ω | ||
VTH_PG | Power Good threshold for external 5-V supply | VV5ANA rising | 4.7 | V | ||
VTH_HYS_PG | Power Good threshold hysteresis for external 5-V supply | VV5ANA falling | 100 | mV | ||
ILKG | Leakage current | Switch disabled, VV5ANA = 5 V, VLDO5 = 0 V |
10 | µA | ||
LDO3P3 | ||||||
VIN | Input voltage at VSYS pin | 5.6 | 13 | 21 | V | |
VOUT | DC output voltage | IOUT = 10 mA | 3.3 | V | ||
Accuracy | VIN = 13 V, IOUT = 10 mA |
–3% | 3% | |||
IOUT | DC output current | 40 | mA | |||
IOCP | Overcurrent protection | Measured with output shorted to ground | 70 | mA | ||
VTH_PG | Power Good assertion threshold in percentage of target VOUT | VOUT rising | 92% | |||
VTH_PG_HYS | Power Good deassertion hysteresis | VOUT falling | 3% | |||
IQ | Quiescent current | VIN = 13 V, IOUT = 0 A |
20 | µA | ||
COUT | External output capacitance | 2.2 | 4.7 | 10 | µF |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
BUCK1, BUCK2, BUCK6 | |||||||
VIN | Power input voltage for external HSD FET | 5.6 | 13 | 21 | V | ||
VOUT | DC output voltage VID range and options | VID step size = 10 mV, BUCKx_VID[6:0] progresses from 0000001 to 1111111 | 0.41 | 1.67 | V | ||
VID step size = 25 mV, BUCKx_VID[6:0] progresses from 0000001 to 1111111 | 1(1) | 3.575 | V | ||||
BUCK1 output voltage | Set by BUCK1_VID[6:0], 10 mV step size selected | 1.05 | V | ||||
BUCK2 output voltage | Set by BUCK2_VID[6:0], 25 mV step size selected | 3.3 | V | ||||
BUCK6 output voltage | Set by BUCK6_VID[6:0], 10 mV step size selected | 1.5 | V | ||||
DC output voltage accuracy | VOUT = 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V, IOUT = 100 mA to 7 A |
–2% | 2% | ||||
Total output voltage accuracy (DC + ripple) in DCM | IOUT = 10 mA, VOUT ≤ 1 V | –30 | 40 | mV | |||
SR(VOUT) | Output DVS slew rate | 2.5 | 3.125 | mV/µs | |||
ILIM_LSD | Low-side output valley current limit accuracy (programmed by external resistor RLIM) | –15% | 15% | ||||
ILIMREF | Source current out of ILIM1 pin | T = 25°C | 45 | 50 | 55 | µA | |
VLIM | Voltage at ILIM1 pin | VLIM = RLIM × ILIMREF | 0.2 | 2.25 | V | ||
ΔVOUT/ΔVIN | Line regulation | VOUT = 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V, IOUT = 7 A |
–0.5% | 0.5% | |||
ΔVOUT/ΔIOUT | Load regulation | VIN = 13 V, VOUT = 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V, IOUT = 0 A to 7 A, referenced to VOUT at IOUT = IOUT_MAX |
0% | 1% | |||
VTH_PG | Power Good deassertion threshold in percentage of target VOUT | VOUT rising | 105.5% | 108% | 110.5% | ||
VOUT falling | 89.5% | 92% | 94.5% | ||||
RDSON_DRVH | Driver DRVH resistance | Source, IDRVH = –50 mA | 3 | Ω | |||
Sink, IDRVH = 50 mA | 2 | Ω | |||||
RDSON_DRVL | Driver DRVL resistance | Source, IDRVL = –50 mA | 3 | Ω | |||
Sink, IDRVL = 50 mA | 0.4 | Ω | |||||
RDIS | Output auto-discharge resistance | BUCK1_DIS[1:0] = 01 | 100 | Ω | |||
BUCK1_DIS[1:0] = 10 | 200 | Ω | |||||
BUCK1_DIS[1:0] = 11 | 500 | Ω | |||||
CBOOT | Bootstrap capacitance | 100 | nF | ||||
RON_BOOT | Bootstrap switch ON resistance | 20 | Ω |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
BUCK3, BUCK4, BUCK5 | ||||||
VIN | Power input voltage | 4.5 | 5 | 5.5 | V | |
VOUT | DC output voltage VID range and options | VID step size = 10 mV, BUCKx_VID[6:0] progresses from 0000001 to 1111111 | 0.41 | 1.67 | V | |
VID step size = 12.5 mV, BUCKx_VID[6:0] progresses from 0000001 to 1111111 | 0.4125 | 1.9875 | ||||
VID step size = 25 mV, BUCKx_VID[6:0] progresses from 0000001 to 1111111 | 0.425 | 3.575 | ||||
BUCK3 output voltage | Set by BUCK3_VID[6:0], 25-mV step size selected | 1.05 | V | |||
BUCK4 output voltage | Set by BUCK4_VID[6:0], 25-mV step size selected | 3.3 | ||||
BUCK5 output voltage | Set by BUCK5_VID[6:0], 25-mV step size selected | 1.5 | ||||
DC output voltage accuracy | VOUT = 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V, IOUT = 1.5 A |
–2% | 2% | |||
VOUT = 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V, IOUT = 100 mA |
–2.5% | 2.5% | ||||
Total output voltage accuracy (DC + ripple) in DCM | IOUT = 10 mA, VOUT ≤ 1 V | –30 | 40 | mV | ||
SR(VOUT) | Output DVS slew rate | 2.5 | 3.125 | mV/µs | ||
IOUT | Continuous DC output current | 3 | A | |||
IIND_LIM | HSD FET current limit | 4.3 | 7 | A | ||
IQ | Quiescent current | VIN = 5 V, VOUT = 1 V | 35 | µA | ||
ΔVOUT/ΔVIN | Line regulation | VOUT = 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V, IOUT = 1.5 A |
–0.5% | 0.5% | ||
ΔVOUT/ΔIOUT | Load regulation | VIN = 5 V, VOUT = 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V, IOUT = 0 A to 3 A, referenced to VOUT at IOUT = 1.5 A |
–0.2% | 2% | ||
VTH_PG | Power Good deassertion threshold in percentage of target VOUT | VOUT rising | 108% | |||
VOUT falling | 92% | |||||
VTH_HYS_PG | Power Good reassertion hysteresis entering back into VTH_PG | VOUT rising or falling | 3% | |||
RDIS | Output auto-discharge resistance | BUCK3_DIS[1:0] = 01 | 100 | Ω | ||
BUCK3_DIS[1:0] = 10 | 200 | |||||
BUCK3_DIS[1:0] = 11 | 500 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
LDOA1 | ||||||
VIN | Input voltage | 4.5 | 5 | 5.5 | V | |
VOUT | DC output voltage | Set by LDOAx_VID[3:0] | 3.3 | |||
Accuracy | IOUT = 0 to 200 mA | –2% | 2% | V | ||
IOUT | DC output current | 200 | mA | |||
ΔVOUT/ΔVIN | Line regulation | IOUT = 40 mA | –0.5% | 0.5% | ||
ΔVOUT/ΔIOUT | Load regulation | IOUT = 10 mA to 200 mA | –2% | 2% | ||
IOCP | Overcurrent protection | VIN = 5 V, Measured with output shorted to ground | 500 | mA | ||
VTH_PG | Power Good deassertion threshold in percentage of target VOUT | VOUT rising | 108% | |||
VOUT falling | 92% | |||||
tSTARTUP | Start-up time | Measured from EN = H to reach 95% of final value, COUT = 4.7 µF |
500 | µs | ||
IQ | Quiescent current | IOUT = 0 A | 23 | µA | ||
COUT | External output capacitance | 2.7 | 4.7 | 10 | µF | |
ESR | 100 | mΩ | ||||
RDIS | Output auto-discharge resistance | LDOA1_DIS[1:0] = 01 | 100 | Ω | ||
LDOA1_DIS[1:0] = 10 | 190 | Ω | ||||
LDOA1_DIS[1:0] = 11 | 450 | Ω | ||||
LDOA2 and LDOA3 | ||||||
VIN | Power input voltage | VOUT + VDROP (1) | 1.8 | 1.98 | V | |
VOUT | LDOA2 DC output voltage | Set by LDOAx_VID[3:0] | 0.7 | V | ||
LDOA3 DC output voltage | Set by LDOAx_VID[3:0] | 1.2 | V | |||
DC output voltage accuracy | IOUT = 0 to 600 mA | –2% | 3% | |||
IOUT | DC output current | 600 | mA | |||
VDROP | Dropout voltage | VOUT = 0.99 × VOUT_NOM, IOUT = 600 mA |
350 | mV | ||
ΔVOUT/ΔVIN | Line regulation | IOUT = 300 mA | –0.5% | 0.5% | ||
ΔVOUT/ΔIOUT | Load regulation | IOUT = 10 mA to 600 mA | –2% | 2% | ||
IOCP | Overcurrent protection | Measured with output shorted to ground | 0.65 | 1.25 | A | |
VTH_PG | Power Good assertion threshold in percentage of target VOUT | VOUT rising | 108% | |||
VOUT falling | 92% | |||||
tSTARTUP | Start-up time | Measured from EN = H to reach 95% of final value, COUT = 4.7 µF | 500 | µs | ||
IQ | Quiescent current | IOUT = 0 A | 20 | µA | ||
LDOA2 and LDOA3 (continued) | ||||||
PSRR | Power supply rejection ratio | f = 1 kHz, VIN = 1.8 V, VOUT = 1.2 V, IOUT = 300 mA, COUT = 2.2 µF – 4.7 µF |
48 | dB | ||
f = 10 kHz, VIN = 1.8 V, VOUT = 1.2 V, IOUT = 300 mA, COUT = 2.2 µF – 4.7 µF |
30 | dB | ||||
COUT | External output capacitance | 2.2 | 4.7 | 10 | µF | |
ESR | 100 | mΩ | ||||
RDIS | Output auto-discharge resistance | LDOA2_DIS[1:0] = 01 | 80 | Ω | ||
LDOA2_DIS[1:0] = 10 | 180 | |||||
LDOA2_DIS[1:0] = 11 | 475 | |||||
VTT LDO | ||||||
VIN | Power input voltage | 1.2 | 3.3 | V | ||
VOUT | DC output voltage | VIN = 1.2 V, Measured at VTTFB pin | VIN / 2 | V | ||
DC output voltage accuracy | Relative to VIN / 2, IOUT ≤ 10 mA, 1.1 V ≤ VIN ≤ 1.35 V |
–10 | 10 | mV | ||
Relative to VIN / 2, IOUT ≤ 500 mA, 1.1 V ≤ VIN ≤ 1.35 V |
–25 | 25 | ||||
IOUT | DC output current | sink(–) and source(+) | –500 | 500 | mA | |
ΔVOUT/ΔIOUT | Load regulation | 1.1 V ≤ VIN ≤ 1.35 V, IOUT = –500 mA to 500 mA |
–4% | 4% | ||
IOCP | Overcurrent protection | Measured with output shorted to ground | 0.95 | A | ||
VTH_PG | Power Good deassertion threshold in percentage of target VOUT | VOUT rising | 110% | |||
VOUT falling | 95% | |||||
VTH_HYS_PG | Power Good reassertion hysteresis entering back into VTH_PG | 5% | ||||
IQ | Total ground current | VIN = 1.2 V, IOUT = 0 A | 240 | µA | ||
ILKG | OFF leakage current | VIN = 1.2 V, disabled | 1 | µA | ||
CIN | External input capacitance | 10 | µF | |||
COUT | External output capacitance | 35 | µF | |||
RDIS | Output auto-discharge resistance | VTT_DIS = 0 | 1000 | kΩ | ||
VTT_DIS = 1 | 60 | 80 | 100 | Ω |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SWA1 | ||||||
VIN | Input voltage range | 0.5 | 1.8 | 3.3 | V | |
IOUT | DC output current | 300 | mA | |||
RDSON | ON resistance | VIN = 1.8 V, measured from PVINSWA1 pin to SWA1 pin at IOUT = IOUT,MAX | 60 | 93 | mΩ | |
VIN = 3.3 V, measured from PVINSWA1 pin to SWA1 pin at IOUT = IOUT,MAX | 100 | 165 | ||||
VTH_PG | Power Good deassertion threshold in percentage of target VOUT | VOUT rising | 108% | |||
VOUT falling | 92% | |||||
VTH_HYS_PG | Power Good reassertion hysteresis entering back into VTH_PG | VOUT rising or falling | 2% | |||
IINRUSH | Inrush current upon turnon | VIN = 3.3 V, COUT = 0.1 µF | 10 | mA | ||
IQ | Quiescent current | VIN = 3.3 V, IOUT = 0 A | 10.5 | µA | ||
VIN = 1.8 V, IOUT = 0 A | 9 | |||||
ILKG | Leakage current | Switch disabled, VIN = 1.8 V | 7 | 370 | nA | |
Switch disabled, VIN = 3.3 V | 10 | 900 | ||||
COUT | External output capacitance | 0.1 | µF | |||
RDIS | Output auto-discharge resistance | SWA1_DIS[1:0] = 01 | 100 | Ω | ||
SWA1_DIS[1:0] = 10 | 200 | |||||
SWA1_DIS[1:0] = 11 | 500 | |||||
SWB1_2 | ||||||
VIN | Input voltage range | 0.5 | 1.8 | 3.3 | V | |
IOUT | DC current per output | 400 | mA | |||
RDSON | ON resistance | VIN = 1.8 V, measured from PVINSWB1_B2 pin to SWB1/SWB2 pin at IOUT = IOUT,MAX | 68 | 92 | mΩ | |
VIN = 3.3 V, measured from PVINSWB1_B2 pin to SWB1/SWB2 pin at IOUT = IOUT,MAX | 75 | 125 | mΩ | |||
VTH_PG | Power Good deassertion threshold in percentage of target VOUT | VOUT rising | 108% | |||
VOUT falling | 92% | |||||
VTH_HYS_PG | Power Good reassertion hysteresis entering back into VTH_PG | VOUT rising or falling | 2% | |||
IINRUSH | Inrush current upon turning on | VIN = 3.3 V, COUT = 0.1 µF | 10 | mA | ||
IQ | Quiescent current | VIN = 3.3 V, IOUT = 0 A | 10.5 | µA | ||
VIN = 1.8 V, IOUT = 0 A | 9 | |||||
ILKG | Leakage current | Switch disabled, VIN = 1.8 V | 7 | 460 | nA | |
Switch disabled, VIN = 3.3 V | 10 | 1150 | ||||
COUT | External output capacitance | 0.1 | µF | |||
RDIS | Output auto-discharge resistance | SWBx_DIS[1:0] = 01 | 100 | Ω | ||
SWBx_DIS[1:0] = 10 | 200 | |||||
SWBx_DIS[1:0] = 11 | 500 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VOL | Low-level output voltage | VPULL_UP = 1.8 V | 0.4 | V | ||
VIH | High-level input voltage | 1.2 | V | |||
VIL | Low-level input voltage | 0.4 | V | |||
ILKG | Leakage current | VPULL_UP = 1.8 V | 0.01 | 0.3 | µA | |
RPULL-UP | Pullup resistance | Standard mode | 8.5 | kΩ | ||
Fast mode | 2.5 | |||||
Fast mode plus | 1 | |||||
COUT | Total load capacitance per pin | 50 | pF |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VIH | High-level input voltage | 0.85 | V | |||
VIL | Low-level input voltage | 0.4 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VOL | Low-level output voltage | IOL < 2 mA | 0.4 | V | ||
ILKG | Leakage current | VPULL_UP = 1.8 V | 0.35 | µA |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
I2C INTERFACE | |||||
fCLK | Clock frequency (standard mode) | 100 | kHz | ||
Clock frequency (fast mode) | 400 | kHz | |||
Clock frequency (fast mode plus) | 1000 | kHz | |||
tr | Rise time (standard mode) | 1000 | ns | ||
Rise time (fast mode) | 300 | ns | |||
Rise time (fast mode plus) | 120 | ns | |||
tf | Rise time (standard mode) | 300 | ns | ||
Rise time (fast mode) | 300 | ns | |||
Rise time (fast mode plus) | 120 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
BUCK CONTROLLERS | ||||||
tPG | Total turnon time | Measured from enable going high to when output reaches 90% of target value. | 550 | 850 | µs | |
TON,MIN | Minimum on-time of DRVH | 50 | ns | |||
TDEAD | Driver dead-time | DRVH off to DRVL on | 15 | ns | ||
DRVL off to DRVH on | 30 | ns | ||||
fSW | Switching frequency | Continuous-conduction mode, VIN = 13 V, VOUT ≥ 1 V |
1000 | kHz | ||
BUCK CONVERTERS | ||||||
tPG | Total turnon time | Measured from enable going high to when output reaches 90% of target value. | 250 | 1000 | µs | |
fSW | Switching frequency | Continuous-conduction mode, VOUT = 1 V, IOUT = 1 A | 1.7 | MHz | ||
Continuous-conduction mode, VOUT = 1.05 V, IOUT = 1 A | 1.9 | MHz | ||||
Continuous-conduction mode, VOUT = 1.8 V, IOUT = 1 A | 2.5 | MHz | ||||
LDOAx | ||||||
tSTARTUP | Start-up time | Measured from enable going high to when output reaches 95% of final value, VOUT = 1.2 V, COUT = 4.7 µF |
180 | µs | ||
VTT LDO | ||||||
tSTARTUP | Start-up time | Measured from enable going high to PG assertion, VOUT = 0.675 V, COUT = 40 µF |
22 | µs | ||
SWA1 | ||||||
tTURN-ON | Turnon time | Measured from enable going high to reach 95% of final value, VIN = 3.3 V, COUT = 0.1 µF |
0.85 | ms | ||
Measured from enable going high to reach 95% of final value, VIN = 1.8 V, COUT = 0.1 µF |
0.63 | ms | ||||
SWB1_2 | ||||||
tTURN-ON | Turnon time | Measured from enable going high to reach 95% of final value, VIN = 3.3 V, COUT = 0.1 µF |
1.1 | ms | ||
Measured from enable going high to reach 95% of final value, VIN = 1.8 V, COUT = 0.1 µF |
0.82 | ms |