SLVS774C June   2007  – January 2016 TPS650240 , TPS650241 , TPS650242 , TPS650243 , TPS650244 , TPS650245

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: Control Signals and Supply Pins
    6. 7.6  Electrical Characteristics: VDCDC1 Step-Down Converter
    7. 7.7  Electrical Characteristics: VDCDC2 Step-Down Converter
    8. 7.8  Electrical Characteristics: VDCDC3 Step-Down Converter
    9. 7.9  Electrical Characteristics: General
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Step-Down Converters, VDCDC1, VDCDC2 and VDCDC3
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Save Mode Operation
      2. 8.4.2 Soft-Start
      3. 8.4.3 100% Duty Cycle Low-Dropout Operation
      4. 8.4.4 Low-Dropout Voltage Regulators
      5. 8.4.5 Undervoltage Lockout
      6. 8.4.6 Power-Up Sequencing
      7. 8.4.7 PWRFAIL
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Output Voltage Selection
      2. 9.1.2 Voltage Change on VDCDC3
      3. 9.1.3 Vdd_alive Output
      4. 9.1.4 LDO1 and LDO2
      5. 9.1.5 VCC Filter
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Configuration for the Samsung Processor S3C6400-533MHz
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Inductor Selection for the DC-DC Converters
          2. 9.2.1.2.2 Output Capacitor Selection
          3. 9.2.1.2.3 Input Capacitor Selection
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Typical Configuration for the Titan 2 Processor
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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11 Layout

11.1 Layout Guidelines

  • The input capacitors for the DC-DC converters must be placed as close as possible to the VINDCDCx and VCC pins.
  • The inductor of the output filter must be placed as close as possible to the device to provide the shortest switch node possible, reducing the noise emitted into the system and increasing the efficiency.
  • Sense the feedback voltage of the output at the output capacitors to ensure the best DC accuracy. Feedback must be routed away from noisy sources such as the inductor. If possible route on the opposite side from the switch node and inductor and place a GND plane between the feedback and the noisy sources or a keep-out underneath them entirely.
  • Place the output capacitors as close as possible to the inductor to reduce the feedback loop. This ensures the best regulation at the feedback point.
  • Place the device as close as possible to the most demanding or sensitive load. The output capacitors must be placed close to the input of the load. This ensures the best AC performance possible.
  • The input and output capacitors for the LDOs must be placed close to the device for best regulation performance.
  • Use vias to connect thermal pad to ground plane.
  • A common ground plane is recommended for the layout of this device. The AGND can be separated from the PGND, but a large low-parasitic PGND is required to connect the PGNDx pins to the CIN and external PGND connections. If the AGND and PGND planes are separated, have one connection point to reference the grounds together. Place this connection point close to the IC.

11.2 Layout Example

TPS650240 TPS650241 TPS650242 TPS650243 TPS650244 TPS650245 TPS65024x Layout Callouts.jpg Figure 23. Layout Diagram