SLVS667B July   2006  – January 2016 TPS65022

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VRTC Output and Operation With or Without Backup Battery
      2. 7.3.2  Step-Down Converters, VDCDC1, VDCDC2, and VDCDC3
      3. 7.3.3  Power Save Mode Operation
      4. 7.3.4  Low Ripple Mode
      5. 7.3.5  Soft-Start
      6. 7.3.6  100% Duty Cycle Low Dropout Operation
      7. 7.3.7  Active Discharge When Disabled
      8. 7.3.8  Power Good Monitoring
      9. 7.3.9  Low Dropout Voltage Regulators
      10. 7.3.10 Undervoltage Lockout
      11. 7.3.11 Power-Up Sequencing
      12. 7.3.12 System Reset + Control Signals
        1. 7.3.12.1 DEFLDO1 and DEFLDO2
        2. 7.3.12.2 Interrupt Management and the INT Pin
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
    6. 7.6 Register Maps
      1. 7.6.1 VERSION Register Address: 00h (read only)
      2. 7.6.2 PGOODZ Register Address: 01h (read only)
      3. 7.6.3 MASK Register Address: 02h (read/write) Default Value: C0h
      4. 7.6.4 REG_CTRL Register Address: 03h (read/write) Default Value: FFh
      5. 7.6.5 CON_CTRL Register Address: 04h (read/write) Default Value: B1h
      6. 7.6.6 CON_CTRL2 Register Address: 05h (read/write) Default Value: 40h
      7. 7.6.7 DEFCORE Register Address: 06h (read/write) Default Value: 14h/1Eh
      8. 7.6.8 DEFSLEW Register Address: 07h (read/write) Default Value: 06h
      9. 7.6.9 LDO_CTRL Register Address: 08h (read/write) Default Value: set with DEFLDO1 and DEFLDO2
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Voltage Connection
      2. 8.1.2 Unused Regulators
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection for the DC-DC Converters
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Output Voltage Selection
        5. 8.2.2.5 VRTC Output
        6. 8.2.2.6 LDO1 and LDO2
        7. 8.2.2.7 TRESPWRON
        8. 8.2.2.8 VCC-Filter
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VI Input voltage range on all pins except AGND and PGND pins with respect to AGND –0.3 7 V
Current at VINDCDC1, L1, PGND1, VINDCDC2, L2, PGND2, VINDCDC3, L3, PGND3 2000 mA
Peak current at all other pins 1000 mA
TA Operating free-air temperature –40 85 °C
TJ Maxiumum junction temperature 125 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Input voltage range step-down convertors (VINDCDC1, VINDCDC2, VINDCDC3);
pins need to be tied to the same voltage rail		 2.5 6 V
VO Output voltage range for VDCDC1 step-down convertor(1) 0.6 VINDCDC1 V
Output voltage range for VDCDC2 (mem) step-down convertor(1) 0.6 VINDCDC2
Output voltage range for VDCDC3 (core) step-down convertor(1) 0.6 VINDCDC3
VI Input voltage range for LDOs (VINLDO1, VINLDO2) 1.5 6.5 V
VO Output voltage range for LDOs (VLDO1, VLDO2) 1 VINLDO1-2 V
IO(DCDC2) Output current at L1 1200 mA
Inductor at L1(2) 2.2 3.3 μH
CI(DCDC1) Input capacitor at VINDCDC1 (2) 10 μF
CO(DCDC1) Output capacitor at VDCDC1 (2) 10 22 μF
IO(DCDC2) Output current at L2 1000 mA
Inductor at L2 (2) 2.2 3.3 μH
CI(DCDC2) Input capacitor at VINDCDC2 (2) 10 μF
CO(DCDC2) Output capacitor at VDCDC2 (2) 10 22 μF
IO(DCDC3) Output current at L3 900 mA
Inductor at L3 (2) 2.2 3.3 μH
CI(DCDC3) Input capacitor at VINDCDC3(2) 10 μF
CO(DCDC3) Output capacitor at VDCDC3 (2) 10 22 μF
CI(VCC) Input capacitor at VCC (2) 1 μF
Ci(VINLDO) Input capacitor at VINLDO (2) 1 μF
CO(VLDO1-2) Output capacitor at VLDO1, VLDO2 (2) 2.2 μF
IO(VLDO1-2) Output current at VLDO1, VLDO2 200 mA
CO(VRTC) Output capacitor at VRTC (2) 4.7 μF
TA Operating ambient temperature –40 85 °C
TJ Operating junction temperature –40 125 °C
Resistor from VINDCDC3, VINDCDC2, VINDCDC1 to VCC used for filtering(3) 1 10 Ω
(1) When using an external resistor divider at DEFDCDC3, DEFDCDC2, DEFDCDC1
(2) See Application and Implementation for more information.
(3) Up to 3 mA can flow into VCC when all 3 converters are running in PWM. This resistor causes the UVLO threshold to be shifted accordingly.

6.4 Thermal Information

THERMAL METRIC(1) TPS65022 UNIT
RHA (VQFN)
40 PINS
RθJA Junction-to-ambient thermal resistance 31.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 18.2 °C/W
RθJB Junction-to-board thermal resistance 6.6 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 6.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CONTROL SIGNALS : SCLK, SDAT (input), DCDC1_EN, DCDC2_EN, DCDC3_EN, LDO_EN, DEFLDO1, DEFLDO2
VIH High level input voltage Rpullup at SCLK and SDAT = 4.7 kΩ, pulled to VRTC 1.3 VCC V
VIL Low level input voltage Rpullup at SCLK and SDAT = 4.7 kΩ, pulled to VRTC 0 0.4 V
IH Input bias current 0.01 0.1 μA
CONTROL SIGNALS : HOT_RESET
VIH High level input voltage 1.3 VCC V
VIL Low level input voltage 0 0.4 V
IIB Input bias current 0.01 0.1 μA
tdeglitch Deglitch time at HOT_RESET 25 30 35 ms
CONTROL SIGNALS : LOWBAT, PWRFAIL, RESPWRON, INT, SDAT (output)
VOH High level output voltage 6 V
VOL Low level output voltage IIL = 5 mA 0 0.3 V
Duration of low pulse at RESPWRON External capacitor 1 nF 100 ms
ICONST internal charge and discharge current on pin TRESPWRON used for generating RESPWRON delay 1.7 2 2.3 μA
TRESPWRON_LOWTH internal lower comparator threshold on pin TRESPWRON used for generating RESPWRON delay 0.225 0.25 0.275 V
TRESPWRON_UPTH internal upper comparator threshold on pin TRESPWRON used for generating RESPWRON delay 0.97 1 1.103 V
Resetpwron threshold VRTC falling –3% 2.4 3% V
Resetpwron threshold VRTC rising –3% 2.52 3% V
ILK leakage current output inactive high 0.1 μA
SUPPLY PINS: VCC, VINDCDC1, VINDCDC2, VINDCDC3
I(q) Operating quiescent current, PFM VCC = 3.6 V,
VBACKUP = 3 V;
V(VSYSIN) = 0 V		 All 3 DCDC converters enabled,
zero load and no switching, LDOs enabled		 85 100 μA
All 3 DCDC converters enabled,
zero load and no switching, LDOs off		 78 90
DCDC1 and DCDC2 converters enabled,
zero load and no switching, LDOs off		 57 70
DCDC1 converter enabled,
zero load and no switching, LDOs off		 43 55
II Current into VCC; PWM VCC = 3.6 V,
VBACKUP = 3 V;
V(VSYSIN) = 0 V		 All 3 DCDC converters enabled and
running in PWM, LDOs off		 2 3 mA
DCDC1 and DCDC2 converters enabled and
running in PWM, LDOs off		 1.5 2.5
DCDC1 converter enabled and
running in PWM, LDOs off		 0.85 2
I(q) Quiescent current All converters disabled, LDOs off,
V(VSYSIN) = 0 V		 VCC = 3.6 V, VBACKUP = 3 V 23 33 μA
VCC = 2.6 V, VBACKUP = 3 V 3.5 5
VCC = 3.6 V, VBACKUP = 0 V 43
SUPPLY PINS: VBACKUP, VSYSIN, VRTC
I(q) Operating quiescent current VBACKUP = 3 V, VSYSIN = 0 V; VCC = 2.6 V,
current into VBACKUP		 20 33 μA
I(SD) Operating quiescent current VBACKUP < V_VBACKUP, current into VBACKUP 2 3 μA
VRTC LDO output voltage VSYSIN = VBACKUP = 0 V, IO = 0 mA 3 V
IO Output current for VRTC VSYSIN < 2.57 V and VBACKUP < 2.57 V 30 mA
VRTC short-circuit current limit VRTC = GND; VSYSIN = VBACKUP = 0 V 100 mA
Maximum output current at VRTC for
RESPWRON = 1		 VRTC > 2.6 V, VCC = 3 V; VSYSIN = VBACKUP = 0 V 30 mA
VO Output voltage accuracy for VRTC VSYSIN = VBACKUP = 0 V; IO = 0 mA –1% 1%
Line regulation for VRTC VCC = VRTC + 0.5 V to 6.5 V, IO = 5 mA –1% 1%
Load regulation VRTC IO = 1 mA to 30 mA; VSYSIN = VBACKUP = 0 V –3% 1%
Regulation time for VRTC Load change from 10% to 90% 10 μs
Ilkg Input leakage current at VSYSIN VSYSIN < V_VSYSIN 2 μA
rDS(on) of VSYSIN switch 12.5 Ω
rDS(on) of VBACKUP switch 12.5 Ω
Input voltage range at VBACKUP(1) 2.73 3.75 V
Input voltage range at VSYSIN(1) 2.73 3.75 V
VSYSIN threshold VSYSIN falling –3% 2.55 3% V
VSYSIN threshold VSYSIN rising –3% 2.65 3% V
VBACKUP threshold VBACKUP falling –3% 2.55 3% V
VBACKUP threshold VBACKUP falling –3% 2.65 3% V
SUPPLY PIN: VINLDO
I(q) Operating quiescent current Current per LDO into VINLDO 16 30 μA
I(SD) Shutdown current Total current for both LDOs into VINLDO, VLDO = 0 V 0.1 1 μA
VDCDC1 STEP-DOWN CONVERTER
VI Input voltage range, VINDCDC1 2.5 6 V
IO Maximum output current 1200 mA
I(SD) Shutdown supply current in VINDCDC1 DCDC1_EN = GND 0.1 1 μA
rDS(on) P-channel MOSFET on-resistance VINDCDC1 = V(GS) = 3.6 V 125 261 mΩ
Ilkg P-channel leakage current VINDCDC1 = 6 V 2 μA
rDS(on) N-channel MOSFET on-resistance VINDCDC1 = V(GS) = 3.6 V 130 260 mΩ
Ilkg N-channel leakage current V(DS) = 6 V 7 10 μA
Forward current limit (P- and N-channel) 2.5 V < VI(MAIN) < 6 V 1.55 1.75 1.95 A
fS Oscillator frequency 1.3 1.5 1.7 MHz
Fixed output voltage FPWMDCDC1 = 0 3 V VINDCDC1 = 3.3 V to 6 V; 0 mA ≤ IO  ≤ 1.2 A –2% 2%
3.3 V VINDCDC1 = 3.6 V to 6 V; 0 mA ≤ IO  ≤ 1.2 A –2% 2%
Fixed output voltage FPWMDCDC1 = 1 3 V VINDCDC1 = 3.3 V to 6 V; 0 mA ≤ IO  ≤ 1.2 A –1% 1%
3.3 V VINDCDC1 = 3.6 V to 6 V; 0 mA ≤ IO  ≤ 1.2 A –1% 1%
Adjustable output voltage with resistor divider at DEFDCDC1; FPWMDCDC1 = 0 VINDCDC1 = VDCDC1 + 0.3 V (min 2.5 V) to 6 V;
0 mA ≤ IO  ≤ 1.2 A		 –2% 2%
Adjustable output voltage with resistor divider at DEFDCDC1; FPWMDCDC1 = 1 VINDCDC1 = VDCDC1 + 0.3 V (min 2.5 V) to 6 V;
0 mA ≤ IO  ≤ 1.2 A		 –1% 1%
Line Regulation VINDCDC1 = VDCDC1 + 0.3 V (min 2.5 V) to 6 V;
IO = 10 mA		 0 %/V
Load Regulation IO = 10 mA to 1200 mA 0.25 %/A
Soft start ramp time VDCDC1 ramping from 5% to 95% of target value 750 μs
Internal resistance from L1 to GND 1 MΩ
VDCDC1 discharge resistance DCDC1 discharge = 1 300 Ω
VDCDC2 STEP-DOWN CONVERTER
VI Input voltage range, VINDCDC2 2.5 6 V
IO Maximum output current 1000 mA
I(SD) Shutdown supply current in VINDCDC2 DCDC2_EN = GND 0.1 1 μA
rDS(on) P-channel MOSFET on-resistance VINDCDC2 = V(GS) = 3.6 V 140 300 mΩ
Ilkg P-channel leakage current VINDCDC2 = 6 V 2 μA
rDS(on) N-channel MOSFET on-resistance VINDCDC2 = V(GS) = 3.6 V 150 297 mΩ
Ilkg N-channel leakage current V(DS) = 6 V 7 10 μA
ILIMF Forward current limit (P- and N-channel) 2.5 V < VINDCDC2 < 6 V 1.4 1.55 1.7 A
fS Oscillator frequency 1.3 1.5 1.7 MHz
Fixed output voltage FPWMDCDC2 = 0 1.8 V VINDCDC2 = 2.5 V to 6 V; 0 mA ≤ IO  ≤ 1 A –2% 2%
2.5 V VINDCDC2 = 2.8 V to 6 V; 0 mA ≤ IO  ≤ 1 A –2% 2%
Fixed output voltage FPWMDCDC2 = 1 1.8 V VINDCDC2 = 2.5 V to 6 V; 0 mA ≤ IO  ≤ 1 A –2% 2%
2.5 V VINDCDC2 = 2.8 V to 6 V; 0 mA ≤ IO  ≤ 1 A –1% 1%
Adjustable output voltage with resistor divider at DEFDCDC2 FPWMDCDC2 = 0 VINDCDC2 = VDCDC2 + 0.3 V (min 2.5 V) to 6 V;
0 mA ≤ IO  ≤ 1 A		 –2% 2%
Adjustable output voltage with resistor divider at DEFDCDC2; FPWMDCDC2 = 1 VINDCDC2 = VDCDC2 + 0.3 V (min 2.5 V) to 6 V;
0 mA ≤ IO  ≤ 1 A		 –1% 1%
Line Regulation VINDCDC2 = VDCDC2 + 0.3 V (min 2.5 V) to 6 V;
IO = 10 mA		 0 %/V
Load Regulation IO = 10 mA to 1 mA 0.25 %/A
Soft start ramp time VDCDC2 ramping from 5% to 95% of target value 750 μs
Internal resistance from L2 to GND 1 MΩ
VDCDC2 discharge resistance DCDC2 discharge =1 300 Ω
VDCDC3 STEP-DOWN CONVERTER
VI Input voltage range, VINDCDC3 2.5 6 V
IO Maximum output current 900 mA
I(SD) Shutdown supply current in VINDCDC3 DCDC3_EN = GND 0.1 1 μA
rDS(on) P-channel MOSFET on-resistance VINDCDC3 = V(GS) = 3.6 V 310 698 mΩ
Ilkg P-channel leakage current VINDCDC3 = 6 V 0.1 2 μA
rDS(on) N-channel MOSFET on-resistance VINDCDC3 = V(GS) = 3.6 V 220 503 mΩ
Ilkg N-channel leakage current V(DS) = 6 V 7 10 μA
Forward current limit (P- and N-channel) 2.5 V < VINDCDC3 < 6 V 1.15 1.34 1.52 A
fS Oscillator frequency 1.3 1.5 1.7 MHz
Fixed output voltage FPWMDCDC3 = 0 All VDCDC3 VINDCDC3 = 2.5 V to 6 V; 0 mA ≤ IO  ≤ 800 mA –2% 2%
Fixed output voltage FPWMDCDC3 = 1 All VDCDC3 VINDCDC3 = 2.5 V to 6 V; 0 mA ≤ IO  ≤ 800 mA –1% 1%
Adjustable output voltage with resistor divider at DEFDCDC3 FPWMDCDC3 = 0 VINDCDC3 = VDCDC3 + 0.5 V (min 2.5 V) to 6 V;
0 mA ≤ IO  ≤ 800 mA		 –2% 2%
Adjustable output voltage with resistor divider at DEFDCDC3; FPWMDCDC3 = 1 VINDCDC3 = VDCDC3 + 0.5 V (min 2.5 V) to 6 V;
0 mA ≤ IO  ≤ 800 mA		 –1% 1%
Line Regulation VINDCDC3 = VDCDC3 + 0.3 V (min 2.5 V) to 6 V;
IO = 10 mA		 0 %/V
Load Regulation IO = 10 mA to 400 mA 0.25 %/A
Soft start ramp time VDCDC3 ramping from 5% to 95% of target value 750 μs
Internal resistance from L3 to GND 1 MΩ
VDCDC3 discharge resistance DCDC3 discharge =1 300 Ω
VLDO1 and VLDO2 LOW DROPOUT REGULATORS
VI Input voltage range for LDO1, 2 1.5 6.5 V
VO LDO1 output voltage range 1 3.3 V
VO LDO2 output voltage range 1 3.3 V
IO Maximum output current for LDO1, LDO2 VI = 1.8 V, VO = 1.3 V 200 mA
VI = 1.5 V, VO = 1.3 V 120
I(SC) LDO1 and LDO2 short circuit current limit V(LDO1) = GND, V(LDO2) = GND 400 mA
Minimum voltage drop at LDO1, LDO2 IO = 50 mA, VINLDO = 1.8 V 120 mV
IO = 50 mA, VINLDO = 1.5 V 65 150
IO = 200 mA, VINLDO = 1.8 V 300
Output voltage accuracy for LDO1, LDO2 IO = 10 mA –2% 1%
Line regulation for LDO1, LDO2 VINLDO1,2 = VLDO1,2 + 0.5 V
(min 2.5 V) to 6.5 V, IO = 10 mA		 –1% 1%
Load regulation for LDO1, LDO2 IO = 0 mA to 50 mA –1% 1%
Regulation time for LDO1, LDO2 Load change from 10% to 90% 10 μs
ANALOGIC SIGNALS DEFDCDC1, DEFDCDC2, DEFDCDC3
VIH High level input voltage 1.3 VCC V
VIL Low level input voltage 0 0.1 V
Input bias current 0.001 0.05 μA
THERMAL SHUTDOWN
T(SD) Thermal shutdown Increasing junction temperature 160 °C
Thermal shutdown hysteresis Decreasing junction temperature 20 °C
INTERNAL UNDERVOLTAGE LOCK OUT
UVLO Internal UVLO VCC falling –2% 2.35 2% V
V(UVLO_HYST) Internal UVLO comparator hysteresis 120 mV
VOLTAGE DETECTOR COMPARATORS
Comparator threshold (PWRFAIL_SNS, LOWBAT_SNS) Falling threshold –1% 1 1% V
Hysteresis 40 50 60 mV
Propagation delay 25 mV overdrive 10 μs
POWER GOOD
V(PGOODF) VDCDC1, VDCDC2, VDCDC3, VLDO1, VLDO2, decreasing –12% –10% –8%
V(PGOODR) VDCDC1, VDCDC2, VDCDC3, VLDO1, VLDO2, increasing –7% –5% –3%
(1) Based on the requirements for the Intel PXA270 processor.

Timing Requirements

VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 2.5 V to 5.5 V, VBACKUP = 3 V, TA = –40°C to 85°C.
MIN MAX UNIT
fMAX Clock frequency 400 kHz
twH(HIGH) Clock high time 600 ns
twL(LOW) Clock low time 1300 ns
tR DATA and CLK rise time 300 ns
tF DATA and CLK fall time 300 ns
th(STA) Hold time (repeated) START condition (after this period the first clock pulse is generated) 600 ns
th(DATA) Setup time for repeated START condition 600 ns
th(DATA) Data input hold time 0 ns
tsu(DATA) Data input setup time 100 ns
tsu(STO) STOP condition setup time 600 ns
t(BUF) Bus free time 1300 ns
TPS65022 hot_timing_lvs607.gif Figure 1. HOT_RESET Timing
TPS65022 pu_pd_time_lvs613.gif Figure 2. Power-Up and Power-Down Timing
TPS65022 dvs_timing_lvs613.gif Figure 3. DVS Timing

6.6 Typical Characteristics

Table 1. Table of Graphs

FIGURE
Efficiency vs Output current Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10
Line transient response Figure 11, Figure 12, Figure 13
Load transient response Figure 14, Figure 15, Figure 16
Output voltage ripple Figure 17, Figure 18, Figure 19
Startup Figure 20, Figure 21
Line transient response Figure 22, Figure 23, Figure 24
Load transient response Figure 25, Figure 26, Figure 27
TPS65022 eff_33v1_io_lvs607.gif Figure 4. DCDC1: Efficiency vs Output Current
TPS65022 eff_18v1_io_lvs607.gif Figure 6. DCDC2: Efficiency vs Output Current
TPS65022 eff_155v1_io_lvs607.gif Figure 8. DCDC3: Efficiency vs Output Current
TPS65022 eff_13v1_io_lvs607.gif Figure 10. DCDC3: Efficiency vs Output Current
TPS65022 vdcdc2_lt_lvs613.gif Figure 12. VDCDC2 Line Transient Response
TPS65022 vdcdc1_ld_lvs613.gif Figure 14. VDCDC1 Load Transient Response
TPS65022 vdcdc3_ld_lvs613.gif Figure 16. VDCDC3 Load Transient Response
TPS65022 vdcdc2_vo2_lvs607.gif Figure 18. VDCDC2 Output Voltage Ripple
TPS65022 startup_vdc_lvs607.gif Figure 20. Startup VDCDC1, VDCDC2, and VDCDC3
TPS65022 ldo1_lt_lvs613.gif Figure 22. LDO1 Line Transient Response
TPS65022 vrtc_lt_lvs613.gif Figure 24. VRTC Line Transient Response
TPS65022 ldo2_ld_lvs613.gif Figure 26. LDO2 Load Transient Response
TPS65022 eff_33v2_io_lvs607.gif Figure 5. DCDC1: Efficiency vs Output Current
TPS65022 eff_18v2_io_lvs607.gif Figure 7. DCDC2: Efficiency vs Output Current
TPS65022 eff_155v2_io_lvs607.gif Figure 9. DCDC3: Efficiency vs Output Current
TPS65022 vdcdc1_lt_lvs613.gif
Figure 11. VDCDC1 Line Transient Response
TPS65022 vdcdc3_lt_lvs613.gif Figure 13. VDCDC3 Line Transient Response
TPS65022 vdcdc2_ld_lvs613.gif Figure 15. VDCDC2 Load Transient Response
TPS65022 vdcdc2_vo1_lvs613.gif Figure 17. VDCDC2 Output Voltage Ripple
TPS65022 vdcdc2_vo3_lvs613.gif Figure 19. VDCDC2 Output Voltage Ripple
TPS65022 startup_ldo_lvs607.gif Figure 21. Startup LDO1 and LDO2
TPS65022 ldo2_lt_lvs613.gif Figure 23. LDO2 Line Transient Response
TPS65022 ldo1_ld_lvs613.gif Figure 25. LDO1 Load Transient Response
TPS65022 vrtc_ld_lvs613.gif Figure 27. VRTC Load Transient Response