SLVS551A December   2004  – September 2015 TPS65014

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics: Battery Charger
    7. 6.7  Dissipation Ratings
    8. 6.8  Serial Interface Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Step-Down Converters, VMAIN and VCORE
        1. 7.3.1.1 Forced PWM
        2. 7.3.1.2 Dynamic Voltage Positioning
        3. 7.3.1.3 Soft-Start
        4. 7.3.1.4 100% Duty Cycle Low Dropout Operation
        5. 7.3.1.5 Active Discharge When Disabled
        6. 7.3.1.6 Power-Good Monitoring
        7. 7.3.1.7 Overtemperature Shutdown
      2. 7.3.2 Low-Dropout Voltage Regulators
        1. 7.3.2.1 Power-Good Monitoring
        2. 7.3.2.2 Enabling and Sequencing
      3. 7.3.3 Undervoltage Lockout
      4. 7.3.4 Power-Up Sequencing
        1. 7.3.4.1 TPS65014 Power State Descriptions
          1. 7.3.4.1.1 State 1: No Power
          2. 7.3.4.1.2 State 2: ON
          3. 7.3.4.1.3 State 3: Low-Power Mode
          4. 7.3.4.1.4 State 4: Shutdown
      5. 7.3.5 System Reset and Control Signals
      6. 7.3.6 Vibrator Driver
      7. 7.3.7 LED2 Output
      8. 7.3.8 Interrupt Management
      9. 7.3.9 Serial Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Save Mode Operation
      2. 7.4.2 Sleep Mode
    5. 7.5 Register Maps
      1. 7.5.1  CHGSTATUS Register (offset = 01h) (reset: 00h)
      2. 7.5.2  REGSTATUS Register (offset = 02h) (reset: 00h)
      3. 7.5.3  MASK1 Register (offset = 03h) (reset: FFh)
      4. 7.5.4  MASK2 Register (offset = 04h) (reset: FFh)
      5. 7.5.5  ACKINT1 Register (offset = 05h) (reset: 00h)
      6. 7.5.6  ACKINT2 Register (offset: 06h) (reset: 00h)
      7. 7.5.7  CHGCONFIG Register (offset: 07h) (reset: 1Bh)
      8. 7.5.8  LED1_ON Register (offset: 08h) (reset: 00h)
      9. 7.5.9  LED1_PER Register (offset: 09h) (reset: 00h)
      10. 7.5.10 LED2_ON Register (offset: 0Ah) (reset: 00h)
      11. 7.5.11 LED2_PER (offset: 0Bh) (reset: 00h)
      12. 7.5.12 VDCDC1 Register (offset: 0Ch) (reset: 32h/33h)
      13. 7.5.13 VDCDC2 Register (offset: 0Dh) (reset: 60h/70h)
      14. 7.5.14 VREGS1 Register (offset: 0Eh) (reset: 88h)
      15. 7.5.15 MASK3 Register (offset: 0Fh) (reset: 00h)
      16. 7.5.16 DEFGPIO Register (offset = 10h) (reset: 00h)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection for the Main and the Core Converter
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Battery Charger
      1. 9.1.1 Autonomous Power Source Selection
      2. 9.1.2 Temperature Qualification
      3. 9.1.3 Battery Preconditioning
      4. 9.1.4 Battery Charge Current
      5. 9.1.5 Battery Voltage Regulation
      6. 9.1.6 Charge Termination and Recharge
      7. 9.1.7 PG Output
      8. 9.1.8 Thermal Considerations for Setting Charge Current
    2. 9.2 LDO1 Output Voltage Adjustment
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

10 Layout

10.1 Layout Guidelines

  • The input capacitors for the DC-DC converters must be placed as close as possible to the VINMAIN, VINCORE, and VCC pins.
  • The inductor of the output filter must be placed as close as possible to the device to provide the shortest switch node possible, thus reducing the noise emitted into the system and increasing the efficiency.
  • Sense the feedback voltage from the output at the output capacitors to ensure the best DC accuracy. Feedback must be routed away from noisy sources such as the inductor. If possible, route on the opposite side from the switch node and inductor, and place a GND plane between the feedback and the noisy sources or keepout underneath them entirely.
  • Place the output capacitors as close as possible to the inductor to reduce the feedback loop. This ensures best regulation at the feedback point.
  • Place the device as close as possible to the most demanding or sensitive load. The output capacitors must be placed close to the input of the load, which ensures the best AC performance possible.
  • The input and output capacitors for the LDOs must be placed close to the device for best regulation performance.
  • Use vias to connect the thermal pad to the ground plane.
  • TI recommends using the common ground plane for the layout of this device. The AGND can be separated from the PGND, but a large low-parasitic PGND is required to connect the PGNDx pins to the CIN and external PGND connections. If the AGND and PGND planes are separated, have one connection point to reference the grounds together. Place this connection point close to the IC.

10.2 Layout Example

TPS65014 layout_ex_slvs551.gif Figure 61. Layout Recommendation