ZHCSEQ2A February   2016  – February 2016 TPS62480

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable / Shutdown (EN)
      2. 7.3.2  Soft Start (SS), Pre-biased Output
      3. 7.3.3  Tracking (TR)
      4. 7.3.4  Output Voltage Select (VSEL)
      5. 7.3.5  Forced PWM (MODE)
      6. 7.3.6  Power Good (PG)
      7. 7.3.7  Thermal Good (TG)
      8. 7.3.8  Active Output Discharge
      9. 7.3.9  Undervoltage Lockout (UVLO)
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pulse Width Modulation (PWM) Operation
      2. 7.4.2 Power Save Mode (PSM) Operation
      3. 7.4.3 Minimum Duty Cycle and 100% Mode Operation
      4. 7.4.4 Phase Shifted Operation
      5. 7.4.5 Phase Add/Shed and Current Balancing
      6. 7.4.6 Current Limit and Short Circuit Protection
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting the Adjustable Output Voltage
        2. 8.2.2.2 Setting VOUT2 Using the VSEL Feature
        3. 8.2.2.3 Output Filter Selection
        4. 8.2.2.4 Inductor Selection
        5. 8.2.2.5 Output Capacitor Selection
        6. 8.2.2.6 Input Capacitor Selection
        7. 8.2.2.7 Soft Start Capacitor Selection
        8. 8.2.2.8 Tracking
        9. 8.2.2.9 Current Sharing
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8 Application and Implementation

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NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

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8.1 Application Information

The TPS62480 is a switched mode step-down converter, able to convert a 2.4-V to 5.5-V input voltage into a lower 0.6-V to 5.5-V output voltage, providing up to 6 A continuous output current. It needs a minimum amount of external components. Apart from the LC output filter and the input capacitors, additional resistors or capacitors are only needed to enable features like soft start, adjustable and selectable output voltage as well as Power Good and/or Thermal Good.

8.2 Typical Application

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TPS62480 SLVSCL9_app.gif
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Figure 6. Typical Application using TPS62480 for a 6A Point-Of-Load Power Supply

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8.2.1 Design Requirements

The following design guideline provides a range for the component selection to operate within the recommended operating conditions. Table 1 shows the components selection that was used for the measurements shown in the Application Curves.

Table 1. List of Components

REFERENCE DESCRIPTION MANUFACTURER
IC 5.5-V, 6-A step-down converter, QFN TPS62480RNC, Texas Instruments
L 2x0.47-µH ±20%, (2.5x2x1.2) mm DFE252012P-R47M, Toko
Cin 2x22-µF, 10-V, ceramic, 0603, X5R GRM188R61A226ME15#, muRata
Cout 4x22-µF, 25-V, ceramic, 0805, X5R GRM21BR61E226ME44L, muRata
Css 3300-pF, 10-V, ceramic, 0402 Standard
R1 Depending on Vout1, chip, 0402, 0.1% Standard
R2 Depending on Vout1, chip, 0402, 0.1% Standard
R3 Depending on Vout2, chip, 0402, 0.1% Standard
R4, R5 470-kΩ, chip, 0603, 1/16-W, 1% Standard

8.2.2 Detailed Design Procedure

8.2.2.1 Setting the Adjustable Output Voltage

While the device regulates the FB voltage to 0,6V, the output voltage is specified from 0.6 to 5.5 V. A resistive divider (from VOUT to FB to AGND) sets the actual output voltage of the TPS62480. Equation 4 and Equation 5 are calculating the values of the resistors. First, determining the current through the resistive divider leads to the total resistance (R1 + R2). A minimum divider current of about 5 µA is recommended and can be higher if needed.

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Equation 4. TPS62480 SLVSCL9_eqvout1.gif
Equation 5. TPS62480 SLVSCL9_eqvout2.gif

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8.2.2.2 Setting VOUT2 Using the VSEL Feature

A VOUT level, different as set with R1 and R2 (see Setting the Adjustable Output Voltage), can be forced by connecting R3 between FB and RS pins and pulling VSEL High. R3 is calculated using Equation 6.

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Equation 6. TPS62480 SLVSCL9_eqvsel.gif

where:

V1 is the lower level output voltage and

V2 the higher level output voltage.

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8.2.2.3 Output Filter Selection

The TPS62480 is internally compensated and optimized to work for a certain range of L-C combinations. The recommended minimum output capacitance is 4 x 22 µF, that can be ceramic capacitors exclusively. A larger value of COUT might be needed for VOUT ≤ 1.8V, to improve transient response performance, as well as for VOUT > 3.3 V to compensate for voltage bias effects of the ceramic capacitors. The other way round, using of an additional feed forward capacitor can help reducing amount of output capacitance that is needed to achieve a certain transient response target (see Output Capacitor Selection).

8.2.2.4 Inductor Selection

The TPS62480 is designed to operate with two inductors of nominal 470 nH each. Inductors must be selected for adequate saturation current and for low dc resistance (DCR). The minimum inductor current rating IL(min) that is needed under static load conditions calculates using Equation 7 and Equation 8. A current imbalance of 10% is incorporated.

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Equation 7. TPS62480 SLVSCL9_eqilmin.gif

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Equation 8. TPS62480 SLVSCL9_eqdeltailmax.gif

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Choosing VIN = 2 VOUT, this calculation provides the minimum saturation current of the inductor needed. Additional margin is recommended to cover dynamic overshoot due to load transients. For low profile solutions, the physical inductor size and the power losses have to be traded off. Smallest solution size gives less efficiency and thermal performance due to larger DCR and/or core losses. The inductors shown in Table 2 have been tested with the TPS62480:

Table 2. List of Inductors

TYPE INDUCTANCE [µH] CURRENT RATING MIN/TYP [A] DCR MAX [mΩ] DIMENSIONS (LxBxH) [mm] MANUFACTURER
ΔL/L = 30% ΔT = 40K
DFE201612E-R47M 0.47 ±20% 5.5/6.1 4.5/5.0 26 2.0 x 1.6 x 1.2 TOKO
DFE252012F-R47M 0.47 ±20% 6.7/7.4 4.9/5.8 22 2.5 x 2.0 x 1.2 TOKO
DFE252010F-R47M 0.47 ±20% 6.0/6.6 4.4/5.2 27 2.5 x 2.0 x 1.0 TOKO
HMLQ25201B-R47MSR-11 0.47 ±20% 5.6/6.2 4.2/4.7 28 2.5 x 2.0 x 1.2 CYNTEC
HMLQ20161T-R47MDR-11 0.47 ±20% 4.4/4.9 4.0/4.4 32 2.0 x 1.6 x 1.0 CYNTEC
GLCLMR4701A 0.47 ±20% 3.6/4.5 3.8/4.7 32 2.5 x 2.0 x 1.2 ALPS
GLCLKR4701A 0.47 ±20% 3.5/4.4 3.7/4.6 38 2.5 x 2.0 x 1.0 ALPS
XFL4015-471ME 0.47 ±20% 6.6 11.2 8.36 4.0 x 4.0 x 1.5 COILCRAFT

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8.2.2.5 Output Capacitor Selection

The TPS62480 provides a wide output voltage range of 0.6 V to 5.5 V. While stability is a critical criteria for the output filter selection, the output capacitor value also determines transient response behavior, ripple and accuracy of VOUT. The internal compensation is designed for an output capacitance range from about 50 µF to 150 µF effectively. Since ceramic capacitors are used preferably, this translates into nominal values of 4 x 22 µF to 4 x 47 µF and mainly depends on the output voltage. The following values are recommended:

Table 3. Recommended Output Capacitor Values (nominal)

VOUT ≤ 1.0V 1.0V ≤ VOUT ≤ 3.3V VOUT ≥ 3.3V
2x22µF
4x22µF √
4x47µF √ √ √
6x47µF

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Beyond the recommendations in Table 3, other values can be chosen and might be suitable depending on VOUT and actual effective capacitance. In such case, stability needs to be checked within the actual environment.

Even if the output capacitance is sufficient for stability, a different value might be desirable to improve the transient response behavior. Table 4 can be used to determine capacitor values for specific transient response targets:

Table 4. Recommended Output Capacitor Values (nominal)

Output Voltage [V] Load Step [A] Output Capacitor Value(1) Feedforward Capacitor(1) Typical Transient Response Accuracy
±mV ±%
1.0 0 - 3 4 x 47µF - 50 5
3 - 6 50 5
1.8 0 - 3 4 x 22µF 36pF 50 3
3 - 6 50 3
2.5 0 - 3 4 x 22µF 36pF 62 2.5
3 - 6 50 2
3.3 0 - 3 4 x 47µF 36pF 100 3
3 - 6 80 2.5
(1) The values in the table are nominal values. The effective capacitance can differ significantly, depending on package size, voltage rating and dielectric material.

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The architecture of the TPS62480 allows the use of tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get narrow capacitance variation with temperature, it is recommended to use X5R or X7R dielectrics. Using even higher values than demanded for stability and transient response has further advantages like smaller voltage ripple and tighter dc output accuracy in Power Save Mode.

8.2.2.6 Input Capacitor Selection

The input current of a buck converter is pulsating. Therefore, a low ESR input capacitor is required to prevent large voltage transients at the source but to provide peak currents to the device. The recommended value for most applications is 2 x 22 µF, split between the VIN1 and VIN2 inputs and placed as close as possible to these pins and PGND pins. If additional capacitance is needed, it can be added as bulk capacitance. To ensure proper operation, the effective capacitance at the VIN pins must not fall below 2 x 5 µF.

Low ESR multilayer ceramic capacitors are recommended for best filtering. Increasing with input voltage, the dc bias effect reduces the nominal capacitance value significantly. To decrease input ripple current further, larger values of input capacitors can be used.

8.2.2.7 Soft Start Capacitor Selection

The soft start ramp time can be set externally connecting a capacitor between the SS/TR and AGND pins. The capacitor value CSS that is needed to get a specific rising time ΔtSS calculates as:

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Equation 9. TPS62480 SLVSCL9_eqtss.gif

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Since the device has an internal delay time ΔtDELAY from EN=High to start switching, the overall startup time is longer as shown in Figure 7.

TPS62480 SLVSCL9_startup.gif Figure 7. Soft Start ΔtSS

If very large output capacitances are used (e.g. >4x47µF), the use of a soft start capacitor is mandatory to secure complete startup.

8.2.2.8 Tracking

For values up to 0.6V, an external voltage, connected to the SS/TR pin, drives the voltage level at the FB pin. In doing so, the voltage at the FB pin is directly proportional to the voltage at the SS/TR pin.

When choosing the resistive divider proportion according to Equation 10, VOUT tracks VTR simultaneously.

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Equation 10. TPS62480 SLVSCL9_eqtr1.gif

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TPS62480 SLVSCL9_tracking.gif Figure 8. Voltage Tracking

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Following the example of Setting the Adjustable Output Voltage with VOUT = 1.8 V, R1 = 240 kΩ and R2 = 120 kΩ, Equation 11 and Equation 12 calculate R3 and R4, connected to the SS/TR pin. Different to the resistive divider at the FB pin, a larger current must be chosen, to avoid a tracking offset caused by the 5.25 µA current that flows out of the SS/TR pin. Assuming a 250 µA current, R4 calculates as follows:

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Equation 11. TPS62480 SLVSCL9_eqtr2.gif

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R3 calculates now rearranging Equation 10:

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Equation 12. TPS62480 SLVSCL9_eqtr3.gif

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However, the following limitations can influence the tracking accuracy:

  • The upper limit of the SS/TR voltage that can be tracked is about 0.6V. Since it is detected internally by a comparator, process variation and ramp speed can cause up to ±30 mV different threshold.
  • In case that the voltage at SS/TR ramps up immediately when VIN is supplied or EN is set High, the internal startup delay, ΔtDELAY, delays the ramp of VOUT. The internal ramp starts after ΔtDELAY at the voltage level, which is actually present at the SS/TR pin.
  • The tracking down speed is limited by the RC time constant of the internal output discharge (always connected when tracking down) and the actual load with the output capacitance. Note: The device tracks down with the same behavior for MODE High (Forced PWM) or Low (Auto PSM).

8.2.2.9 Current Sharing

The TPS62480 is designed to share load current wisely between the 2 phases. The current imbalance is less than 15% over VIN and temperature range and independent on inductor mismatch.

However, the mismatch between the two inductors itself causes additional imbalance of the average inductor currents, caused by different ripple current. The mismatch can be calculated as shown in the following example, assuming that the nominal inductance of 470 nH can vary ±20%, the switching frequency is 2 MHz. Converting 5 V into 2.5 V gives a duty cycle of 0.5, which effects maximum ripple current. Since the ripple current is calculated with:

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Equation 13. TPS62480 SLVSCL9_eqiripple.gif

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the ripple currents in the two inductors are calculated with Iripple1 = 1.69 A and Iripple2 = 1.1 A which gives a ΔIripple of 0.59 A as worst case number based on the maximum inductor tolerance. Figure 9 shows the relation of the two inductor currents in such case.

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TPS62480 SLVSCL9_inductors.gif
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Figure 9. Inductor Currents

The difference in the average current is calculated using:

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Equation 14. TPS62480 SLVSCL9_eqiaverage.gif

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In this worst case calculation the average inductor current mismatch is 0.295A, less than 10% at the full load current of 3A per phase.

Thermal Good

The Thermal Good pin provides an open drain output. The logic level is given by the pull up source which can be VOUT. In this case, TG goes or stays Low, when the device switches off due to EN, UVLO or Thermal Shutdown.

When using an independent source for the pull up logic, the logic behavior at shutdown differs, because the TG pin internally goes high impedance. As before, TG goes Low when TG threshold is reached, but goes back High in the event of being switched off (e.g. Thermal Shutdown).

8.2.3 Application Curves

VIN= 3.6 V, VOUT = 1.8V (R1 / R2 = 240 kΩ / 120 kΩ), TA = 25°C, (unless otherwise noted)

TPS62480 SLVSCL9_eff3.3V_xfl4015.gif
VOUT = 3.3 V
Figure 10. Efficiency vs Output Current
TPS62480 SLVSCL9_eff2.5V_xfl4015.gif
VOUT = 2.5 V
Figure 12. Efficiency vs Output Current
TPS62480 SLVSCL9_eff1.8V_xfl4015.gif
VOUT = 1.8 V
Figure 14. Efficiency vs Output Current
TPS62480 SLVSCL9_eff1.0V_xfl4015.gif
VOUT = 1 V
Figure 16. Efficiency vs Output Current
TPS62480 SLVSCL9_loadreg.gif
Figure 18. Output Voltage vs Output Current
(Load Regulation)
TPS62480 SLVSCL9_IOUTmax_0.6V.gif
VOUT = 0.6 V
Figure 20. Maximum Output Current
TPS62480 SLVSCL9_FSWiout2.5V_lin.gif
VOUT = 2.5 V
Figure 22. Switching Frequency vs Output Current
TPS62480 SLVSCL9_stuplow.gif
VOUT = 1.8 V
Figure 24. Startup into 3.3 Ω
TPS62480 SLVSCL9_discharge2.5V.gif
VOUT = 2.5 V
Figure 26. Output Discharge
TPS62480 SLVSCL9_PWMtyp.gif
Figure 28. Typical Operation PWM
TPS62480 SLVSCL9_ADD2nd.gif
Figure 30. Adding 2nd Phase
TPS62480 SLVSCL9_tran_0-3.gif
Figure 32. Load Transient Response (PSM-PWM),
Load Step 0 to 3 A
TPS62480 SLVSCL9_tran_3-6.gif
Figure 34. Load Transient Response (PWM-PWM),
Load Step 3 to 6 A
TPS62480 SLVSCL9_tran_0-6cff.gif
Cff = 36 pF (nom)
Figure 36. Load Transient Response (PWM-PWM),
Load Step 0 to 6 A
TPS62480 SLVSCL9_thermal18.gif Figure 38. Maximum Ambient Temperature
(TPS62480 EVM)
TPS62480 SLVSCL9_FLIR3.6to1.8V6A.gif
VIN = 3.6 V VOUT = 1.8 V IOUT = 6 A
TA = 25°C
Figure 40. Device Temperature
TPS62480 SLVSCL9_eff3.3V_xfl4015_vin.gif
VOUT = 3.3 V
Figure 11. Efficiency vs Input Voltage
TPS62480 SLVSCL9_eff2.5V_xfl4015_vin.gif
VOUT = 2.5 V
Figure 13. Efficiency vs Input Voltage
TPS62480 SLVSCL9_eff1.8V_xfl4015_vin.gif
VOUT = 1.8 V
Figure 15. Efficiency vs Output Voltage
TPS62480 SLVSCL9_eff1.0V_xfl4015_vin.gif
VOUT = 1 V
Figure 17. Efficiency vs Input Voltage
TPS62480 SLVSCL9_linereg.gif
Figure 19. Output Voltage vs Input Voltage
(Line Regulation)
TPS62480 SLVSCL9_IOUTmax_5.5V.gif
VOUT = 5.5 V
Figure 21. Maximum Output Current
TPS62480 SLVSCL9_FSWiout1.0V_lin.gif
VOUT = 1 V
Figure 23. Switching Frequency vs Output Current
TPS62480 SLVSCL9_stuphigh.gif
VOUT = 1.8 V
Figure 25. Startup into 0.3 Ω
TPS62480 SLVSCL9_discharge1.0V.gif
VOUT = 1 V
Figure 27. Output Discharge
TPS62480 SLVSCL9_PSMtyp.gif
IOUT = 50 mA
Figure 29. Typical Operation PSM
TPS62480 SLVSCL9_SHED2nd.gif
Figure 31. Shedding 2nd Phase
TPS62480 SLVSCL9_tran_0-3cff.gif
Cff = 36 pF (nom)
Figure 33. Load Transient Response (PSM-PWM),
Load Step 0 to 3 A
TPS62480 SLVSCL9_tran_3-6cff.gif
Cff = 36 pF (nom)
Figure 35. Load Transient Response (PWM-PWM),
Load Step 3 to 6 A
TPS62480 SLVSCL9_climfoldback.gif
IOUT = 10 A
Figure 37. Current Limit Fold-Back at Overload
TPS62480 SLVSCL9_thermal33.gif Figure 39. Maximum Ambient Temperature
(TPS62480 EVM)
TPS62480 SLVSCL9_FLIR5to3.3V6A.gif
VIN = 5 V VOUT = 3.3 V IOUT = 6 A
TA = 25°C
Figure 41. Device Temperature

8.3 System Examples

This section provides typical schematics for commonly used output voltages values.

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TPS62480 SLVSCL9_VOUTvar1.gif
Figure 42. A typical 2.5 V & 3.3 V, 6 A Power Supply

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TPS62480 SLVSCL9_VOUTvar2.gif
Figure 43. A typical 1.8 V & 2.5 V, 6 A Power Supply

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TPS62480 SLVSCL9_VOUTvar3.gif
Figure 44. A typical 1.2 V & 1.8 V, 6 A Power Supply

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TPS62480 SLVSCL9_VOUTvar4.gif
Figure 45. A typical 0.9 V & 1 V, 6 A Power Supply

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