• 输入电压范围：1.8V 至 5.5V
• 输出电压范围：2.2V 至 5.5V (TPS61033)
  • FB 连接到 VIN 时，输出电压为固定 5.0V (TPS61033X)
• 两个谷值开关电流限制选项
  • TPS61033：5.5A 典型值
  • TPS610333：1.85A 典型值
• 较高的效率和功率容量
  • 两个 25mΩ (LS)/46mΩ (HS) MOSFET
  • 支持高达 2.4MHz，L-C 较小
  • 效率高达 93.42%（V_IN = 3.3V、V_OUT = 5V 且 I_OUT = 1A 时）
  • 效率高达 90.78%（V_IN = 3.3V、V_OUT = 5V 且 I_OUT = 2A 时）
• 延长系统运行时间
  • 流入 V_IN 引脚的静态电流典型值为 20µA
  • 流入 V_OUT 引脚的静态电流典型值为 5.3μA
  • 关断电流典型值为 0.1μA
• 在 –40°C 至 +125°C 温度范围内，基准电压精度为 ±1.5%
• 具有窗口比较器的电源正常输出
• 可在轻负载下采用引脚可选的自动 PFM 模式或强制 PWM 模式
• V_IN > V_OUT 时切换为直通模式
• 安全、可靠运行的特性
  • 在关断期间真正断开输入域输出之间的连接
  • 输出过压和热关断保护
  • 输出短路保护
• 2.1mm × 1.6mm SOT583 8 引脚封装

• 平板电脑（多媒体）
• 智能扬声器
• 移动 POS

TPS61033X 是一款同步升压转换器。该器件可以为由多种电池和其他电源供电的便携式设备和智能设备提供电源解决方案。在整个温度范围内，TPS61033 具有 5.5A（典型值）谷值开关电流限制，TPS610333 具有 1.85A（典型值）谷值开关电流限制。

TPS61033X 使用自适应恒定导通时间谷值电流控制拓扑来调节输出电压，并在 2.4MHz 开关频率下运行。在轻负载条件下，通过配置 MODE 引脚可实现两种可选模式：自动 PFM 模式和强制 PWM 模式，以便在轻负载条件下实现效率和抗噪性平衡。在轻负载条件下，TPS61033X 通过 V_IN 消耗 20µA 的静态电流。在关断期间，TPS61033X 与输入电源完全断开，仅消耗 0.1µA 的电流，以实现较长的电池寿命。TPS61033X 具有 5.75V 输出过压保护、输出短路保护和热关断保护。

TPS61033X 采用 2.1mm × 1.6mm SOT583 封装，最大限度地减少了外部元件的数量，因而拥有非常小巧的解决方案尺寸。

V_IN = 3.6 V, V_OUT = 5 V, T_J = 25°C, unless otherwise noted

VIN = 2.0 V, 3.3 V, 3.6 V, 4.2 V; L = 0.47 μH, PWM Mode

Figure 7-1 Efficiency vs Output Current V_OUT = 5 V

VIN = 2.0 V, 3.3 V, 3.6 V, 4.2 V; VOUT = 5 V

Figure 7-3 Load Regulation in Auto PWM

VIN = 3.3 V; VOUT = 0 V to 4.5 V

Figure 7-5 Pre-charge Current vs Output Voltage

VIN = 1.8 V, 3.3 V 3.6 V; VOUT = 5 V, TJ = –40°C to +125°C, No switching

Figure 7-7 Quiescent Current into VIN vs Temperature

VIN = VSW = 1.8 V, 3.3 V, 5 V; VOUT = 0 V; TJ = –40°C to +125°C

Figure 7-9 Shutdown Current vs Temperature

VIN = 2.0 V, 3.3 V, 3.6 V, 4.2 V; L = 0.47 μH, Auto PFM Mode

Figure 7-2 Efficiency vs Output Current V_OUT = 5 V

VIN = 2.0 V, 3.3 V, 3.6 V, 4.2 V; VOUT = 5 V

Figure 7-4 Load Regulation in Forced PFM

VIN = 3.3 V; VOUT = 5 V, TJ = –40°C to +125°C

Figure 7-6 Reference Voltage vs Temperature

VIN = 1.8 V; VOUT = 2.2 V, 3.3 V, 5 V, TJ = –40°C to +125°C, No switching

Figure 7-8 Quiescent Current into VOUT vs Temperature

VIN = 3.6 V; VOUT = 5 V; TJ = –40°C to +125°C

Figure 7-10 PGOOD threshold vs Temperature

The TPS61033 is a fully-integrated synchronous boost converter and operates from an input voltage supply range from 1.8 V to 5.5 V with 5.5-A (typical) valley switch current limit. The TPS61033 operates at 2.4-MHz switching frequency. There are two optional modes at light load by configuring the MODE pin: auto PFM mode and forced PWM to balance the efficiency and noise immunity in light load. The TPS61033 consumes an 20-μA quiescent current from VIN at light load condition. During shutdown, the TPS61033 is completely disconnected from the input power and only consumes a 0.1-μA current to achieve long battery life. During PWM operation, the converter uses adaptive constant on-time valley current mode control scheme to achieve excellent line regulation and load regulation and allows the use of a small inductor and ceramic capacitors. Internal loop compensation simplifies the design process while minimizing the number of external components.

The TPS61033 has a built-in undervoltage lockout (UVLO) circuit to ensure the device working properly. When the input voltage is above the UVLO rising threshold of 1.7 V (typical), the TPS61033 can be enabled to boost the output voltage. The device is disabled when the falling voltage at the VIN pin trips the UVLO falling threshold, which is 1.6 V (typical). A hysteresis of 100 mV (typical) is added so that the device cannot be enabled again until the input voltage exceeds 1.7 V (typical). This function is implemented to prevent the device from malfunctioning when the input voltage is between UVLO rising and falling threshold.

When the input voltage is above the UVLO rising threshold and the EN pin is pulled to a voltage above 1.2 V, the TPS61033 is enabled and starts up. To minimize the inrush current during start up, the TPS61033 has a soft start up function. At the beginning, the TPS61033 enters pre-charge phase and charges the output capacitors with a current of approximately 330 mA when the output voltage is below 0.4 V. When the output voltage is charged above 0.4 V, the output current is changed to having output current capability to drive the 2-Ω resistance load. To minimize the inrush current further, the TPS610333 has a maximum pre-charge current of 900 mA(typical). After the output voltage reaches the input voltage, the TPS61033 starts switching, and the reference voltage ramps up a 0.8 mV/μs. When the voltage at the EN pin is below 0.4 V, the internal enable comparator turns the device into shutdown mode. In the shutdown mode, the device is entirely turned off. The output is disconnected from input power supply.

There are two ways to set the output voltage of the TPS61033: adjustable or fixed. If the FB is connected to VIN, the TPS61033 works as a fixed 5.0-V output voltage version, the TPS61033 uses the internal resistor divider.

The output voltage is also can be set by an external resistor divider (R1, R2 in Figure 9-1). When the output voltage is regulated, the typical voltage at the FB pin is V_REF. Thus the resistor divider is determined by Equation 5.

Equation 1.

where

• V_OUT is the regulated output voltage
• V_REF is the internal reference voltage at the FB pin

TPS610333 can only support fixed 5.0-V output voltage, so FB should be connected with VIN rather than external resistor divider.

The TPS61033 uses a valley current limit sensing scheme. Current limit detection occurs during the off-time by sensing of the voltage drop across the synchronous rectifier.

When the load current is increased such that the inductor current is above the current limit within the whole switching cycle time, the off-time is increased to allow the inductor current to decrease to this threshold before the next on-time begins (so called frequency foldback mechanism). When the current limit is reached, the output voltage decreases during further load increase.

The maximum continuous output current (I_OUT(LC)), before entering current limit (CL) operation, can be defined by Equation 2.

Equation 2.

where

• D is the duty cycle
• ΔI_L(P-P) is the inductor ripple current

The duty cycle can be estimated by Equation 3.

Equation 3.

where

• V_OUT is the output voltage of the boost converter
• V_IN is the input voltage of the boost converter
• η is the efficiency of the converter, use 90% for most applications

The peak-to-peak inductor ripple current is calculated by Equation 4.

Equation 4.

where

• L is the inductance value of the inductor
• f_SW is the switching frequency
• D is the duty cycle
• V_IN is the input voltage of the boost converter

When the input voltage is higher than the setting output voltage, the output voltage is higher than the target regulation voltage, the device works in pass-through mode. When the output voltage is 101% of the setting target voltage, the TPS61033 stops switching and fully turns on the high-side PMOS FET. The output voltage is the input voltage minus the voltage drop across the DCR of the inductor and the R_DS(on) of the PMOS FET. When the output voltage drops below the 97% of the setting target voltage as the input voltage declines or the load current increases, the TPS61033 resumes switching again to regulate the output voltage.

The TPS61033 integrates a power good indicator to simplify sequencing and supervision. The power-good output consists of an open-drain NMOS, requiring an external pullup resistor connect to a suitable voltage supply. The PG pin goes high with a typical 1.3 ms delay time after VOUT is between 93% (typical) and 107% (typical) of the target output voltage. When the output voltage is out of the target output voltage window, the PG pin immediately goes low with a 33 μs deglitch filter delay. This deglitch filter also prevents any false pulldown of the PGOOD due to transients. When EN is pulled low, the PG pin is also forced low with a 33 μs deglitch filter delay. If not used, the PG pin can be left floating or connected to GND.

The purpose of the output discharge function is to ensure a defined down-ramp of the output voltage and to let the output voltage close to 0 V quickly when the device is being disabled. TPS61033 can implement output discharge function by PG function that requires a R_Dummy resistor connected between PG pin and Vout pin. PG is an open drain NMOS architecture with up to 50 mA current capability, the PG pin becomes logic high when the output voltage reaches the target value, so the dummy load resistor doesn't lead any power loss during normal operation. When the EN pin gets low, the TPS61033 is disabled and meanwhile the PG pin gets low with a typical 33μs glitch time (t_glitch). With PG pin keeps low, the R_Dummy works as a dummy load to discharge output voltage. Changing R_Dummy can adjust the output discharge rate.

Figure 8-1 Implement Output Discharge by PG function

The TPS61033 has an output overvoltage protection (OVP) to protect the device if the external feedback resistor divider is wrongly populated. When the output voltage is above 5.75 V typically, the device stops switching. Once the output voltage falls 0.1 V below the OVP threshold, the device resumes operating again.

The TPS61033 starts to limit the output current when the output voltage is below 1.8 V. The lower the output voltage reaches, the smaller the output current is. When the VOUT pin is short to ground, and the output voltage becomes less than 0.4 V, the output current is limited to approximately 330 mA. Once the short circuit is released, the TPS61033 goes through the soft start-up again to the regulated output voltage.

The TPS61033 goes into thermal shutdown once the junction temperature exceeds 170°C. When the junction temperature drops below the thermal shutdown recovery temperature, typically 155°C, the device starts operating again.

TPS61033 has two optional modes in light load by configuring the MODE pin: auto PFM mode and forced PWM to balance the efficiency and noise immunity in light load.

The TPS61033 uses a quasi-constant 2.4-MHz frequency pulse width modulation (PWM) at moderate to heavy load current. Based on the input voltage to output voltage ratio, a circuit predicts the required on-time. At the beginning of the switching cycle, the NMOS switching FET. The input voltage is applied across the inductor and the inductor current ramps up. In this phase, the output capacitor is discharged by the load current. When the on-time expires, the main switch NMOS FET is turned off, and the rectifier PMOS FET is turned on. The inductor transfers its stored energy to replenish the output capacitor and supply the load. The inductor current declines because the output voltage is higher than the input voltage. When the inductor current hits the valley current threshold determined by the output of the error amplifier, the next switching cycle starts again.

The TPS61033 has a built-in compensation circuit that can accommodate a wide range of input voltage, output voltage, inductor value, and output capacitor value for stable operation.

The TPS61033 integrates a power-save mode with PFM to improve efficiency at light load. When the load current decreases, the inductor valley current set by the output of the error amplifier no longer regulates the output voltage. When the inductor valley current hits the low limit, the output voltage exceeds the setting voltage as the load current decreases further. When the FB voltage hits the PFM reference voltage, the TPS61033 goes into the power-save mode. In the power-save mode, when the FB voltage rises and hits the PFM reference voltage, the device continues switching for several cycles because of the delay time of the internal comparator — then it stops switching. The load is supplied by the output capacitor, and the output voltage declines. When the FB voltage falls below the PFM reference voltage, after the delay time of the comparator, the device starts switching again to ramp up the output voltage.

Figure 8-2 Output Voltage in PWM Mode and PFM Mode

The TPS61033 is a synchronous boost converter designed to operate from an input voltage supply range between 1.8 V and 5.5 V with a 5.5-A (typical) valley switch current limit. The TPS61033 typically operates at a quasi-constant 2.4-MHz frequency PWM at moderate-to-heavy load currents. At light load currents, the TPS61033 converter operates in power-save mode with PFM to achieve high efficiency over the entire load current range.

The TPS61033 provides a power supply solution for portable devices powered by batteries. With 5.5-A (typical) switch current capability, the TPS61033 can output 5 V and 2 A from a single-cell Li-ion battery.

Figure 9-1 Li-ion Battery to 5-V Boost Converter

The design parameters are listed in Table 9-1.

The output voltage is set by an external resistor divider (R1, R2 in Figure 9-1). When the output voltage is regulated, the typical voltage at the FB pin is V_REF. Thus the resistor divider is determined by Equation 5.

Equation 5.

where

• V_OUT is the regulated output voltage
• V_REF is the internal reference voltage at the FB pin

For the best accuracy, keep R2 smaller than 300 kΩ to ensure the current flowing through R2 is at least 100 times larger than the FB pin leakage current. Changing R2 towards a lower value increases the immunity against noise injection. Changing the R2 towards a higher value reduces the quiescent current for achieving highest efficiency at low load currents.

Because the selection of the inductor affects steady-state operation, transient behavior, and loop stability. The inductor is the most important component in power regulator design. There are three important inductor specifications, inductor value, saturation current, and dc resistance (DCR).

The TPS61033 is designed to work with inductor values between 0.37 µH and 2.9 µH. Follow Equation 6 to Equation 8 to calculate the inductor peak current for the application. To calculate the current in the worst case, use the minimum input voltage, maximum output voltage, and maximum load current of the application. To have enough design margins, choose the inductor value with –30% tolerances, and low power-conversion efficiency for the calculation.

In a boost regulator, the inductor dc current can be calculated by Equation 6.

Equation 6.

where

• V_OUT is the output voltage of the boost converter
• I_OUT is the output current of the boost converter
• V_IN is the input voltage of the boost converter
• η is the power conversion efficiency, use 90% for most applications

The inductor ripple current is calculated by Equation 7.

Equation 7.

where

• D is the duty cycle, which can be calculated by Equation 3
• L is the inductance value of the inductor
• f_SW is the switching frequency
• V_IN is the input voltage of the boost converter

Therefore, the inductor peak current is calculated by Equation 8.

Equation 8.

Normally, it is advisable to work with an inductor peak-to-peak current of less than 40% of the average inductor current for maximum output current. A smaller ripple from a larger valued inductor reduces the magnetic hysteresis losses in the inductor and EMI. But in the same way, load transient response time is increased. The saturation current of the inductor must be higher than the calculated peak inductor current. Table 9-2 lists the recommended inductors for the TPS61033.

The output capacitor is mainly selected to meet the requirements for output ripple and loop stability. The ripple voltage is related to capacitor capacitance and its equivalent series resistance (ESR). Assuming a ceramic capacitor with zero ESR, the minimum capacitance needed for a given ripple voltage can be calculated by Equation 9.

Equation 9.

where

• D_MAX is the maximum switching duty cycle
• V_RIPPLE is the peak-to-peak output ripple voltage
• I_OUT is the maximum output current
• f_SW is the switching frequency

The ESR impact on the output ripple must be considered if tantalum or aluminum electrolytic capacitors are used. The output peak-to-peak ripple voltage caused by the ESR of the output capacitors can be calculated by Equation 10.

Equation 10.

Take care when evaluating the derating of a ceramic capacitor under dc bias voltage, aging, and ac signal. For example, the dc bias voltage can significantly reduce capacitance. A ceramic capacitor can lose more than 50% of its capacitance at its rated voltage. Therefore, always leave margin on the voltage rating to ensure adequate capacitance at the required output voltage. Increasing the output capacitor makes the output ripple voltage smaller in PWM mode.

TI recommends using the X5R or X7R ceramic output capacitor in the range of 4-μF to 1000-μF effective capacitance. The output capacitor affects the small signal control loop stability of the boost regulator. If the output capacitor is below the range, the boost regulator can potentially become unstable. Increasing the output capacitor makes the output ripple voltage smaller in PWM mode.

Multilayer X5R or X7R ceramic capacitors are excellent choices for the input decoupling of the step-up converter as they have extremely low ESR and are available in small footprints. Input capacitors must be located as close as possible to the device. While a 10-μF input capacitor is sufficient for most applications, larger values may be used to reduce input current ripple without limitations. Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, a load step at the output can induce ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or even damage the part. In this circumstance, place additional bulk capacitance (tantalum or aluminum electrolytic capacitor) between ceramic input capacitor and the power source to reduce ringing that can occur between the inductance of the power source leads and ceramic input capacitor.

The device is designed to operate from an input voltage supply range between 1.8 V to 5.5 V. This input supply must be well regulated. If the input supply is located more than a few inches from the converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. A typical choice is a tantalum or aluminum electrolytic capacitor with a value of 100 µF. Output current of the input power supply must be rated according to the supply voltage, output voltage, and output current of the TPS61033.

As for all switching power supplies, especially those running at high switching frequency and high currents, layout is an important design step. If the layout is not carefully done, the regulator suffers from instability and noise problems. To maximize efficiency, switch rise and fall time are very fast. To prevent radiation of high frequency noise (for example, EMI), proper layout of the high-frequency switching path is essential. Minimize the length and area of all traces connected to the SW pin, and always use a ground plane under the switching regulator to minimize interplane coupling. The input capacitor needs not only to be close to the VIN pin, but also to the GND pin in order to reduce input supply ripple.

The most critical current path for all boost converters is from the switching FET, through the rectifier FET, then the output capacitors, and back to ground of the switching FET. This high current path contains nanosecond rise and fall time and must be kept as short as possible. Therefore, the output capacitor not only must be close to the VOUT pin, but also to the GND pin to reduce the overshoot at the SW pin and VOUT pin.

For better thermal performance, TI suggest to make copper polygon connected with each pin bigger.

Restrict the maximum IC junction temperature to 125°C under normal operating conditions. Calculate the maximum allowable dissipation, P_D(max), and keep the actual power dissipation less than or equal to P_D(max). The maximum-power-dissipation limit is determined using Equation 11.

Equation 11.

where

• T_A is the maximum ambient temperature for the application
• R_θJA is the junction-to-ambient thermal resistance given in Section 9.4.3

The TPS61033 comes in a SOT583 package. The real junction-to-ambient thermal resistance of the package greatly depends on the PCB type, layout. Using larger and thicker PCB copper for the power pads (GND, SW, and VOUT) to enhance the thermal performance. Using more vias connects the ground plate on the top layer and bottom layer around the IC without solder mask also improves the thermal capability.