ZHCSCN2 July   2014 TPS57114-EP

PRODUCTION DATA.  

  1. 特性
  2. 应用范围
  3. 说明
  4. 简化电路原理图
  5. 修订历史记录
  6. 说明(续)
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 Handling Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Fixed-Frequency Pwm Control
      2. 9.3.2  Slope Compensation and Output Current
      3. 9.3.3  Bootstrap Voltage (Boot) and Low-Dropout Operation
      4. 9.3.4  Error Amplifier
      5. 9.3.5  Voltage Reference
      6. 9.3.6  Adjusting the Output Voltage
      7. 9.3.7  Enable Functionality and Adjusting UVLO
      8. 9.3.8  Slow-Start or Tracking Pin
      9. 9.3.9  Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      10. 9.3.10 Overcurrent Protection
      11. 9.3.11 Frequency Shift
      12. 9.3.12 Reverse Overcurrent Protection
      13. 9.3.13 Synchronize Using the RT/CLK Pin
      14. 9.3.14 Power Good (PWRGD Pin)
      15. 9.3.15 Overvoltage Transient Protection (OVTP)
      16. 9.3.16 Thermal Shutdown
      17. 9.3.17 Small-Signal Model for Loop Response
      18. 9.3.18 Simple Small-Signal Model for Peak-Current Mode Control
      19. 9.3.19 Small-Signal Model for Frequency Compensation
    4. 9.4 Device Functional Modes
      1. 9.4.1 RT (Resistor Timing) Mode
      2. 9.4.2 CLK (External Clock) Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Sequencing
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Selecting the Switching Frequency
        2. 10.2.2.2 Output Inductor Selection
        3. 10.2.2.3 Output Capacitor
        4. 10.2.2.4 Input Capacitor
        5. 10.2.2.5 Slow-Start Capacitor
        6. 10.2.2.6 Bootstrap Capacitor Selection
        7. 10.2.2.7 Output-Voltage and Feedback-Resistor Selection
        8. 10.2.2.8 Compensation
        9. 10.2.2.9 Power-Dissipation Estimate
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 术语表
  14. 14机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Pin Configuration and Functions

po_RTE-16_SLVSAH5.gif

Pin Functions

PIN DESCRIPTION
NAME NO.
AGND 5 Connect analog ground electrically to GND close to the device.
BOOT 13 The device requires a bootstrap capacitor between BOOT and PH. Having the voltage on this capacitor below the minimum required by the BOOT UVLO forces the output to switch off until the capacitor recharges.
COMP 7 Error amplifier output, and input to the output-switch current comparator. Connect frequency-compensation components to this pin.
EN 15 Enable pin, internal pullup current source. Pull below 1.2 V to disable. Float to enable. An alternative use of this pin can be to set the on-off threshold (adjust UVLO) with two additional resistors.
GND 3 Power ground. Electrically connect this pin directly to the thermal pad under the IC.
4
PH 10 The source of the internal high-side power MOSFET and the drain of the internal low-side (synchronous) rectifier MOSFET
11
12
PWRGD 14 An open-drain output; asserts low if output voltage is low due to thermal shutdown, overcurrent, overvoltage, undervoltage, or EN shutdown.
RT/CLK 8 Resistor-timing or external-clock input pin.
SS/TR 9 Slow start and tracking. An external capacitor connected to this pin sets the output-voltage rise time. Another use of this pin is for tracking.
VIN 1 Input supply voltage, 2.95 to 6 V
2
16
VSENSE 6 Inverting node of the transconductance (gm) error amplifier
Thermal pad Connect the GND pin to the exposed thermal pad for proper operation. Connect this thermal pad to any internal PCB ground plane using multiple vias for good thermal performance.