• 专为耐用的应用而设计
  • 3V 至 18V 输入电压范围
  • 输出电压范围为 0.6V 至 7V
  • 6A 持续输出电流
  • 0.6V ±1% 基准电压 (25°C)
  • 98% 最大占空比
  • 600kHz 开关频率
  • 非闭锁，可提供 OC、OV、UV 和 OT 保护
  • 内置输出放电功能
• 大量兼容引脚的选件
  • 带 SS 引脚可实现可调软启动时间的 TPS566231 和 TPS566238
  • 带 PG 引脚可支持电源正常状态指示器的 TPS566231P 和 TPS566238P
  • 可支持自动跳跃模式的 TPS566231 和 TPS566231P
  • 可支持连续电流模式的 TPS566238 和 TPS566238P
• 提供普通话数据表
• 设计小巧且易于使用
  • 具有 R_DS(on) 20.8mΩ 和 10.6mΩ 的集成功率 MOSFET
  • 可实现快速瞬态响应和内部补偿的 D-CAP3™ 控制模式
  • 1.5mm × 2.0mm HotRod™ QFN 封装
  • 借助 WEBENCH® Power Designer 创建定制设计方案

• 数字电视、机顶盒、游戏机
• 服务器、存储和网络负载点
• 工业 PC、IP 摄像机和工厂自动化应用

TPS56623x 是采用 QFN 9 引脚 1.5mm x 2.0mm 封装的简单、易用且高效的 6A 同步降压转换器。

这些器件采用更宽的电源输入电压范围（3V 至 18V），通过 D-CAP3 控制模式提供快速瞬态响应，具有良好的线路和负载调节，无需外部补偿，并支持低 ESR 输出电容器。

TPS566231 和 TPS566231P 可在 Eco-mode 下运行，从而能在轻载运行期间实现高效率。器件设计为 ULQ™ 直流/直流转换器，可实现 50μA 静态电流，从而在低功耗应用中延长电池寿命。TPS566238 和 TPS566238P 采用连续电流模式运行，可在所有负载条件下保持较低的输出纹波。

TPS566231 和 TPS566238 软启动时间可通过 SS 引脚进行调节。TPS566231P 和 TPS566238P 通过 PG 引脚指示电源正常状态。

TPS56623x 可支持以高达 98% 的占空比运行，并集成了全面的断续模式 OVP、OCP、UVLO、OTP 和 UVP 保护。该器件系列均采用 9 引脚 1.5mm x 2.0mm HotRod 封装。额定结温范围为 -40°C 至 125°C。

The TPS56623x is a 6-A, integrated, FET, synchronous buck converter that operates from 3-V to 18-V input voltage (V_IN) and 0.6-V to 7-V output voltage. The proprietary D-CAP3 control mode enables low external component count, ease of design, and optimization of the power design for cost, size, and efficiency. As the ULQ™ DC/DC converter, the device enables long battery life in system standby mode and high efficiency under light load conditions. The devices employ D-CAP3 control mode that provides fast transient response with no external compensation components and an accurate feedback voltage. The control topology provides a seamless transition between CCM operating mode in heavier load conditions and DCM operation in lighter load conditions.

Eco-mode allows the TPS566231 and TPS566231P to maintain high efficiency at light load. The TPS566238 and TPS566238P work in continuous current mode to maintain lower output ripple in all load conditions. The soft-start time of the TPS566231 and TPS566238 can be adjusted through the SS pin. The TPS566231P and TPS566238P indicate power good through the PG pin. The devices are able to adapt to both low equivalent series resistance (ESR) output capacitors, such as POS-CAP or SP-CAP, and ultra-low ESR ceramic capacitors.

The main control loop of the buck is an adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP3 control mode. D-CAP3 control mode combines adaptive on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. The TPS56623x also includes an error amplifier that makes the output voltage very accurate.

At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after an internal one-shot timer expires. This one-shot duration is set proportional to the output voltage, V_OUT, and is inversely proportional to the converter input voltage, V_IN. This is done to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage. An internal ripple generation circuit is added to the reference voltage to emulate the output ripple. This enables the use of very low-ESR output capacitors such as multi-layered ceramic caps (MLCC). No external current sense network or loop compensation is required for D-CAP3 control mode.

For any control topology that is compensated internally, there is a range of the output filter it can support. The output filter used with the devices is a low-pass L-C circuit. This L-C filter has a double-pole frequency described in Equation 1.

Equation 1.

At low frequency, the overall loop gain is set by the output setpoint resistor divider network and the internal gain of the TPS56623x. The low-frequency L-C double pole has a 180 degree drop in-phase. At the output filter frequency, the gain rolls off at a –40-dB per decade rate and the phase drops rapidly. The internal ripple generation network introduces a high-frequency zero that reduces the gain rolloff from –40-dB to –20-dB per decade and leads the 90 degree phase boost. The internal ripple injection high-frequency zero is approximately 45 kHz. The inductor and capacitor selected for the output filter is recommended such that the double pole is located close to 1/3 the high-frequency zero. This is done so that the phase boost provided by this high-frequency zero provides adequate phase margin for the stability requirement. The crossover frequency of the overall system usually must be targeted to be less than one-third of the switching frequency (F_SW).

The TPS566231 and TPS566238 have an external SS pin to set the soft-start time. When the EN pin becomes high, the soft start function begins ramping up the reference voltage to the PWM comparator.

If the application needs a longer soft-start time than 0.5 ms, the time can be set by connecting a capacitor on the SS pin. When the EN pin becomes high, the soft-start charge current (I_SS) begins charging the external capacitor (C_SS) connected between SS and ground. The devices track the lower of the internal soft-start voltage or the external soft-start voltage as the reference. The estimated equation for the soft-start time (T_SS) is shown in Equation 2:

Equation 2.

where

• V_REF is 0.6 V
• I_SS is 6.5 μA

The TPS566231P and TPS566238P have the PG pin as a power-good indicator. The PG pin is an open-drain output. After the V_FB is between 90% and 110% of the internal reference voltage (V_REF), the PG is de-asserted and floats after a 1-ms de-glitch time. TI recommends a 100-kΩ pullup resistor to pull the voltage up to VCC. The PG pin is pulled low when:

• The FB pin voltage is lower than 85% or greater than 115% of the target output voltage
• The device is in an OVP, UVP, or thermal shutdown event
• Or during the soft-start period

The TPS56623x can support large duty operations by smoothly dropping down the switching frequency. When V_IN / V_OUT < 1.6 and the V_FB is lower than internal V_REF, the switching frequency is allowed to smoothly drop to make T_ON extended. This action is done to implement large duty operation and also improve the performance of the load transient performance. The minimum switching frequency is limited with about 165 kHz with typical 100-ns minimum off-time. The TPS56623x can support up to 98% duty cycle operation.

The TPS56623x has overcurrent protection and undervoltage protection. The output overcurrent limit (OCL) is implemented using a cycle-by-cycle valley detect circuit. The switch current is monitored during the OFF state by measuring the low-side FET drain-to-source voltage. This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.

During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by the following:

• V_IN
• V_OUT
• the on-time
• the output inductor value

There are some important considerations for this type of overcurrent protection. When the load current is higher than the overcurrent threshold by one half of the peak-to-peak inductor ripple current, the OCL is triggered and the current is limited. The output voltage tends to drop because the load demand is higher than what the converter can support. When the output voltage falls below 60% of the target voltage, the UVP comparator detects it and the device shuts off after a 256-μs wait time. The device then restarts after the hiccup time (typically 7 × T_ss). When the overcurrent condition is removed, the output is recovered.