TPS564201 是一款采用 SOT-23 封装的简单易用型 4A 同步降压转换器。
该器件经过优化,最大限度地减少了运行所需的外部组件并且可以实现低待机电流。
这些开关模式电源 (SMPS) 器件采用 D-CAP2 模式控制,能够提供快速瞬态响应,并且在无需外部补偿组件的情况下支持诸如高分子聚合物等低等效串联电阻 (ESR) 输出电容以及超低 ESR 陶瓷电容器。
TPS564201 可在脉冲跳跃模式下运行,从而能在轻载运行期间保持高效率。 TPS564201 采用 6 引脚 1.6-mm × 2.9-mm SOT (DDC) 封装,额定结温范围为 –40°C 至 125°C。
器件型号 | 封装 | 封装尺寸(标称值) |
---|---|---|
TPS564201 | DDC (6) | 1.60mm x 2.90mm |
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Changes from A Revision (May 2016) to B Revision
Changes from * Revision (May 2016) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
GND | 1 | — | Ground pin Source terminal of low-side power NFET as well as the ground terminal for controller circuit. Connect sensitive VFB to this GND at a single point. |
SW | 2 | O | Switch node connection between high-side NFET and low-side NFET. |
VIN | 3 | I | Input voltage supply pin. The drain terminal of high-side power NFET. |
VFB | 4 | I | Converter feedback input. Connect to output voltage with feedback resistor divider. |
EN | 5 | I | Enable input control. Active high and must be pulled up to enable the device. |
VBST | 6 | O | Supply input for the high-side NFET gate drive circuit. Connect 0.1 µF capacitor between VBST and SW pins. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input voltage | VIN, EN | –0.3 | 19 | V |
VBST | –0.3 | 25 | V | |
VBST (10 ns transient) | –0.3 | 27 | V | |
VBST (vs SW) | –0.3 | 6.5 | V | |
VFB | –0.3 | 6.5 | V | |
SW | –2 | 19 | V | |
SW (10 ns transient) | –3.5 | 21 | V | |
Operating junction temperature, TJ | –40 | 150 | °C | |
Storage temperature, Tstg | –55 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±4000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VIN | Supply input voltage range | 4.5 | 17 | V | ||
VI | Input voltage range | VBST | –0.1 | 23 | V | |
VBST (10 ns transient) | –0.1 | 26 | ||||
VBST (vs SW) | –0.1 | 6.0 | ||||
EN | –0.1 | 17 | ||||
VFB | –0.1 | 5.5 | ||||
SW | –1.8 | 17 | ||||
SW (10 ns transient) | –3.5 | 20 | ||||
TJ | Operating junction temperature | –40 | 125 | °C |
THERMAL METRIC(1) | TPS564201 | UNIT | |
---|---|---|---|
DDC (SOT) | |||
6 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 86.3 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 39.4 | °C/W |
RθJB | Junction-to-board thermal resistance | 13.3 | °C/W |
ψJT | Junction-to-top characterization parameter | 1.8 | °C/W |
ψJB | Junction-to-board characterization parameter | 13.3 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
SUPPLY CURRENT | |||||||
IVIN | Operating – non-switching supply current | VIN current, EN = 5 V, VFB = 1 V | TPS564201 | 400 | 510 | µA | |
IVINSDN | Shutdown supply current | VIN current, EN = 0 V | 0.9 | 5 | µA | ||
LOGIC THRESHOLD | |||||||
VENH | EN high-level input voltage | EN | 1.6 | V | |||
VENL | EN low-level input voltage | EN | 0.8 | V | |||
REN | EN pin resistance to GND | VEN = 12 V | 225 | 425 | 900 | kΩ | |
VFB VOLTAGE AND DISCHARGE RESISTANCE | |||||||
VFBTH | VFB threshold voltage | VO = 1.05 V, continuous mode operation | 745 | 760 | 775 | mV | |
IVFB | VFB input current | VFB = 0.8 V | 0 | ±0.1 | µA | ||
MOSFET | |||||||
RDS(on)h | High-side switch resistance | TA = 25°C, VBST – SW = 5.5 V | 50 | mΩ | |||
RDS(on)l | Low-side switch resistance | TA = 25°C | 22 | mΩ | |||
CURRENT LIMIT | |||||||
Iocl | Current limit(1) | DC current, VOUT = 1.05 V, L1 = 1.5 µH | 4.2 | 6 | 7.7 | A | |
THERMAL SHUTDOWN | |||||||
TSDN | Thermal shutdown threshold(1) | Shutdown temperature | 172 | °C | |||
Hysteresis | 38 | ||||||
ON-TIME TIMER CONTROL | |||||||
tOFF(MIN) | Minimum off time | VFB = 0.68 V | 220 | 280 | ns | ||
SOFT START | |||||||
tSS | Soft-start time | Internal soft-start time | 1.0 | ms | |||
FREQUENCY | |||||||
Fsw | Switching frequency | VIN = 12 V, VO = 1.05 V, FCCM mode | 560 | kHz | |||
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION | |||||||
VUVP | Output UVP threshold | Hiccup detect (H > L) | 65% | ||||
THICCUP_WAIT | Hiccup on time | 1.9 | ms | ||||
THICCUP_RE | Hiccup time before restart | 15.5 | ms | ||||
UVLO | |||||||
UVLO | UVLO threshold | Wake up VIN voltage | 4.0 | 4.3 | V | ||
Shutdown VIN voltage | 3.3 | 3.6 | |||||
Hysteresis VIN voltage(1) | 0.4 |
VOUT = 1.05 V | L = 2.2 µH |
VOUT = 1.8 V | L = 2.2 µH |
VOUT = 5 V | L = 3.3 µH |
VOUT = 1.5 V | L = 2.2 µH |
VOUT = 3.3 V | L = 2.2 µH |
The TPS564201 is a 4-A synchronous step-down converter. The proprietary D-CAP2™ mode control supports low ESR output capacitors such as specialty polymer capacitors and multi-layer ceramic capacitors without complex external compensation circuits. The fast transient response of D-CAP2™ mode control can reduce the output capacitance required to meet a specific level of performance.
The main control loop of the TPS564201 is adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2™ mode control. The D-CAP2™ mode control combines adaptive on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one-shot timer expires. This one shot duration is set inversely proportional to the converter input voltage, VIN, and proportional to the output voltage VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2TM mode control.
The TPS564201 is designed with Advanced Eco-mode™ to maintain high light load efficiency. As the output current decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when the zero inductor current is detected. As the load current further decreases the converter runs into discontinuous conduction mode. The on-time is kept almost the same as it was in the continuous conduction mode so that it takes longer time to discharge the output capacitor with smaller load current to the level of the reference voltage. This makes the switching frequency lower, proportional to the load current, and keeps the light load efficiency high. The transition point to the light load operation IOUT(LL) current can be calculated in Equation 1.
The TPS564201 has an internal 1.0-ms soft-start. When the EN pin becomes high, the internal soft-start function begins ramping up the reference voltage to the PWM comparator.
If the output capacitor is pre-biased at startup, the device initiates switching and starts ramping up only after the internal reference voltage becomes greater than the feedback voltage VFB. This scheme ensures that the converter ramps up smoothly into regulation point.
The output over-current limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN, VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the load current Iout. If the monitored current is above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of over-current protection. The load current is higher than the over-current threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being limited, the output voltage tends to fall as the demanded load current may be higher than the current available from the converter. This may cause the output voltage to fall. When the VFB voltage falls below the UVP threshold voltage, the UVP comparator detects it. And then, the device shuts down after the UVP delay time (typically 24 µs) and re-starts after the hiccup time (typically 15.5 ms).
When the over current condition is removed, the output voltage returns to the regulated value.
UVLO protection monitors the internal regulator voltage. When the voltage is lower than UVLO threshold voltage, the device is shut off. This protection is non-latching.
The device monitors the temperature of itself. If the temperature exceeds the threshold value (typically 172°C), the device is shut off. This is a non-latch protection.
When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the TPS564201 operates in the normal switching mode. Normal continuous conduction mode (CCM) occurs when the minimum switch current is above 0 A. In CCM, the TPS564201 operates at a quasi-fixed frequency of 560 kHz.
When the TPS564201 is in the normal CCM operating mode and the switch current falls to 0A, the TPS564201 begins operating in pulse skipping eco-mode. Each switching cycle is followed by a period of energy saving sleep time. The sleep time ends when the VFB voltage falls below the eco-mode threshold voltage. As the output current decreases, the perceived time between switching pulses increases.
When the TPS564201 is operating in either normal CCM or Eco-mode™, it may be placed in standby by asserting the EN pin low.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The device is a typical step-down DC-DC converter for converting a higher dc voltage to a lower dc voltage with a maximum available output current of 4 A. The following design procedure can be used to select component values for the TPS564201. Alternately, the WEBENCH® software may be used to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. This section presents a simplified discussion of the design process.
The application schematic in Figure 14 shows the TPS564201 4.5-V to 17-V input, 1.05-V output converter design meeting the requirements for 4-A output. This circuit is available as the evaluation module (EVM). The sections provide the design procedure.
Table 1 shows the design parameters for this application.
PARAMETER | EXAMPLE VALUE |
---|---|
Input voltage range | 4.5 to 17 V |
Output voltage | 1.05 V |
Transient response, 2-A load step | ΔVout = ±5% |
Input ripple voltage | 400 mV |
Output ripple voltage | 30 mV |
Output current rating | 4 A |
Operating frequency | 560 kHz |
Click here to create a custom design using the TPS564201 device with the WEBENCH® Power Designer.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability.
In most cases, these actions are available:
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends to use 1% tolerance or better divider resistors. Start by using to calculate VOUT.
To improve efficiency at very light loads consider using larger value resistors. However, using too high of resistance causes the circuit to be more susceptible to noise; and, voltage errors from the VFB input current will be more noticeable.
The LC filter used as the output filter has double pole at:
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the device. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high frequency zero that reduces the gain roll off to –20 dB per decade and increases the phase to 90° one decade above the zero frequency. The inductor and capacitor for the output filter must be selected so that the double pole of Equation 3 is located below the high frequency zero but close enough that the phase boost provided be the high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the values recommended in Table 2.
OUTPUT VOLTAGE (V) | R1 (kΩ) | R2 (kΩ) | L1 (µH) | C8 + C9 (µF) | ||
---|---|---|---|---|---|---|
MIN | TYP | MAX | ||||
1 | 3.09 | 10.0 | 1.5 | 2.2 | 4.7 | 20 to 68 |
1.05 | 3.74 | 10.0 | 1.5 | 2.2 | 4.7 | 20 to 68 |
1.2 | 5.76 | 10.0 | 1.5 | 2.2 | 4.7 | 20 to 68 |
1.5 | 9.53 | 10.0 | 1.5 | 2.2 | 4.7 | 20 to 68 |
1.8 | 13.7 | 10.0 | 1.5 | 2.2 | 4.7 | 20 to 68 |
2.5 | 22.6 | 10.0 | 2.2 | 2.2 | 4.7 | 20 to 68 |
3.3 | 33.2 | 10.0 | 2.2 | 2.2 | 4.7 | 20 to 68 |
5 | 54.9 | 10.0 | 3.3 | 3.3 | 4.7 | 20 to 68 |
6.5 | 75 | 10.0 | 3.3 | 3.3 | 4.7 | 20 to 68 |
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4, Equation 5, and Equation 6. The inductor saturation current rating must be greater than the calculated peak current and the RMS or heating current rating must be greater than the calculated RMS current.
Use 560 kHz for ƒSW. Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS current of Equation 7.
For this design example, the calculated peak current is 4.4 A and the calculated RMS current is 4 A. The inductor used is a WE 74431122 with a peak current rating of 13 A and an RMS current rating of 9 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS564201 is intended for use with ceramic or other low ESR capacitors. Recommended values range from 20 µF to 68 µF. Use Equation 7 to determine the required RMS current rating for the output capacitor.
For this design two TDK C3216X5R0J226M 22-µF output capacitors are used. The typical ESR is 2 mΩ each. The calculated RMS current is 0.286 A and each output capacitor is rated for 4 A.
The TPS564201 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. TI recommends a ceramic capacitor over 10 µF for the decoupling capacitor. An additional 0.1-µF capacitor (C3) from pin 3 to ground is optional to provide additional high frequency filtering. The capacitor voltage rating needs to be greater than the maximum input voltage.
A 0.1-µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. TI recommends to use a ceramic capacitor.
VIN = 5 V | VOUT = 1.05 V |
1 µs/div | ||
1 µs/div | ||
100 µs/div | ||
100 µs/div | ||
400 µs/div | ||
VIN = 12 V | VOUT = 1.05 V |
VOUT = 1.05 V |
1 µs/div | ||
1 µs/div | ||
100 µs/div | ||
2 ms/div | ||
The TPS564201 is designed to operate from input supply voltage in the range of 4.5 V to 17 V. Buck converters require the input voltage to be higher than the output voltage for proper operation. The maximum recommended operating duty cycle is 75%. Using that criteria, the minimum recommended input voltage is VO / 0.75.
请单击此处,结合使用 TPS564201 器件和 WEBENCH® 电源设计器创建定制设计方案。
WEBENCH Power Designer 提供一份定制原理图以及罗列实时价格和组件可用性的物料清单。
在多数情况下,可执行以下操作:
有关 WEBENCH 工具的详细信息,请访问 www.ti.com/WEBENCH。
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D-CAP2, Eco-mode, E2E are trademarks of Texas Instruments.
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