TPS564201 采用 SOT-23 封装的 4.5V 至 17V 输入、4A 同步降压稳压器

7.3.1 Adaptive On-Time Control and PWM Operation

The main control loop of the TPS564201 is adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2™ mode control. The D-CAP2™ mode control combines adaptive on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.

At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one-shot timer expires. This one shot duration is set inversely proportional to the converter input voltage, V_IN, and proportional to the output voltage V_O, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2^TM mode control.

7.3.2 Pulse Skip Mode

The TPS564201 is designed with Advanced Eco-mode™ to maintain high light load efficiency. As the output current decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when the zero inductor current is detected. As the load current further decreases the converter runs into discontinuous conduction mode. The on-time is kept almost the same as it was in the continuous conduction mode so that it takes longer time to discharge the output capacitor with smaller load current to the level of the reference voltage. This makes the switching frequency lower, proportional to the load current, and keeps the light load efficiency high. The transition point to the light load operation IOUT(LL) current can be calculated in Equation 1.

Equation 1.

7.3.3 Soft Start and Pre-Biased Soft Start

The TPS564201 has an internal 1.0-ms soft-start. When the EN pin becomes high, the internal soft-start function begins ramping up the reference voltage to the PWM comparator.

If the output capacitor is pre-biased at startup, the device initiates switching and starts ramping up only after the internal reference voltage becomes greater than the feedback voltage V_FB. This scheme ensures that the converter ramps up smoothly into regulation point.

7.3.4 Current Protection

The output over-current limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.

During the on time of the high-side FET switch, the switch current increases at a linear rate determined by V_IN, V_OUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the load current Iout. If the monitored current is above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.

There are some important considerations for this type of over-current protection. The load current is higher than the over-current threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being limited, the output voltage tends to fall as the demanded load current may be higher than the current available from the converter. This may cause the output voltage to fall. When the VFB voltage falls below the UVP threshold voltage, the UVP comparator detects it. And then, the device shuts down after the UVP delay time (typically 24 µs) and re-starts after the hiccup time (typically 15.5 ms).

When the over current condition is removed, the output voltage returns to the regulated value.

7.3.5 Undervoltage Lockout (UVLO) Protection

UVLO protection monitors the internal regulator voltage. When the voltage is lower than UVLO threshold voltage, the device is shut off. This protection is non-latching.

7.3.6 Thermal Shutdown

The device monitors the temperature of itself. If the temperature exceeds the threshold value (typically 172°C), the device is shut off. This is a non-latch protection.

7.4.1 Normal Operation

When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the TPS564201 operates in the normal switching mode. Normal continuous conduction mode (CCM) occurs when the minimum switch current is above 0 A. In CCM, the TPS564201 operates at a quasi-fixed frequency of 560 kHz.

7.4.2 Eco-mode™ Operation

When the TPS564201 is in the normal CCM operating mode and the switch current falls to 0A, the TPS564201 begins operating in pulse skipping eco-mode. Each switching cycle is followed by a period of energy saving sleep time. The sleep time ends when the VFB voltage falls below the eco-mode threshold voltage. As the output current decreases, the perceived time between switching pulses increases.

7.4.3 Standby Operation

When the TPS564201 is operating in either normal CCM or Eco-mode™, it may be placed in standby by asserting the EN pin low.

8.2.1 Design Requirements

Table 1 shows the design parameters for this application.

8.2.2 Detailed Design Procedure

8.2.2.2 Output Voltage Resistors Selection

The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends to use 1% tolerance or better divider resistors. Start by using to calculate V_OUT.

To improve efficiency at very light loads consider using larger value resistors. However, using too high of resistance causes the circuit to be more susceptible to noise; and, voltage errors from the VFB input current will be more noticeable.

Equation 2.

8.2.2.3 Output Filter Selection

The LC filter used as the output filter has double pole at:

Equation 3.

At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the device. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high frequency zero that reduces the gain roll off to –20 dB per decade and increases the phase to 90° one decade above the zero frequency. The inductor and capacitor for the output filter must be selected so that the double pole of Equation 3 is located below the high frequency zero but close enough that the phase boost provided be the high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the values recommended in Table 2.

Table 2. Recommended Component Values

OUTPUT VOLTAGE (V)	R1 (kΩ)	R2 (kΩ)	L1 (µH)			C8 + C9 (µF)
			MIN	TYP	MAX
1	3.09	10.0	1.5	2.2	4.7	20 to 68
1.05	3.74	10.0	1.5	2.2	4.7	20 to 68
1.2	5.76	10.0	1.5	2.2	4.7	20 to 68
1.5	9.53	10.0	1.5	2.2	4.7	20 to 68
1.8	13.7	10.0	1.5	2.2	4.7	20 to 68
2.5	22.6	10.0	2.2	2.2	4.7	20 to 68
3.3	33.2	10.0	2.2	2.2	4.7	20 to 68
5	54.9	10.0	3.3	3.3	4.7	20 to 68
6.5	75	10.0	3.3	3.3	4.7	20 to 68

The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4, Equation 5, and Equation 6. The inductor saturation current rating must be greater than the calculated peak current and the RMS or heating current rating must be greater than the calculated RMS current.

Use 560 kHz for ƒ_SW. Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS current of Equation 7.

Equation 4.

Equation 5.

Equation 6.

For this design example, the calculated peak current is 4.4 A and the calculated RMS current is 4 A. The inductor used is a WE 74431122 with a peak current rating of 13 A and an RMS current rating of 9 A.

The capacitor value and ESR determines the amount of output voltage ripple. The TPS564201 is intended for use with ceramic or other low ESR capacitors. Recommended values range from 20 µF to 68 µF. Use Equation 7 to determine the required RMS current rating for the output capacitor.

Equation 7.

For this design two TDK C3216X5R0J226M 22-µF output capacitors are used. The typical ESR is 2 mΩ each. The calculated RMS current is 0.286 A and each output capacitor is rated for 4 A.

8.2.3 Application Curves

VIN = 5 V

VOUT = 1.05 V

Figure 15. Load Regulation, V_IN = 5 V

Figure 17. Line Regulation

1 µs/div

Figure 19. TPS564201 Input Voltage Ripple

1 µs/div

Figure 21. TPS564201 Output Voltage Ripple, I_OUT 2 A

	100 µs/div

Figure 23. TPS564201 Transient Response 0.1 to 2 A

	100 µs/div

Figure 25. TPS564201 Transient Response, 2 to 4 A

	400 µs/div

Figure 27. TPS564201 Startup Relative to EN

A.

Figure 29. TPS564201 Shutdown Relative to EN

VIN = 12 V

VOUT = 1.05 V

Figure 16. Load Regulation, V_IN = 12 V

VOUT = 1.05 V

Figure 18. Efficiency vs Output Current

1 µs/div

Figure 20. TPS564201 Output Voltage Ripple, No Load

1 µs/div

Figure 22. TPS564201 Output Voltage Ripple, I_OUT 4 A

	100 µs/div

Figure 24. TPS564201 Transient Response, 1 to 3 A

	2 ms/div

Figure 26. TPS564201 Startup Relative to V_IN

Figure 28. TPS564201 Shutdown Relative to V_IN

11.1.1 使用 WEBENCH® 工具创建定制设计方案

请单击此处，结合使用 TPS564201 器件和 WEBENCH® 电源设计器创建定制设计方案。

1. 在开始阶段键入输出电压 (V_IN)、输出电压 (V_OUT) 和输出电流 (I_OUT) 要求。
2. 使用优化器拨盘优化关键设计参数，如效率、封装和成本。
3. 将生成的设计与德州仪器 (TI) 的其他解决方案进行比较。

WEBENCH Power Designer 提供一份定制原理图以及罗列实时价格和组件可用性的物料清单。

在多数情况下，可执行以下操作：

• 运行电气仿真，观察重要波形以及电路性能
• 运行热性能仿真，了解电路板热性能
• 将定制原理图和布局方案导出至常用 CAD 格式
• 打印设计方案的 PDF 报告并与同事共享

有关 WEBENCH 工具的详细信息，请访问 www.ti.com/WEBENCH。