10.1 Layout Guidelines

• Place input capacitors next to the VIN pin and on the same side as the device. Use wide and short traces or copper planes for the connection from the VIN pin to the input capacitor and from the input capacitor to the power pad of the device.
• Place the BP decoupling capacitor close to the BP pin and on the same side as the device in order to avoid the use of vias. Use wide and short traces for the connection from the BP pin to the capacitor and from the capacitor to the power pad. If vias are not evitable, use at least three vias to reduce the parasitic inductance.
• Include a Kelvin VDD connection, or separate from VIN connection (bypass input capacitors); add a placeholder for a filter resistor between the VDD pin and the input bus. Place the VDD decoupling capacitor near the VDD pin and on the same side as the device to avoid the use of vias. Use wide and short traces for the connection from the VDD pin to the capacitor and from the capacitor to the power pad of the device. If vias are not avoidable, use at least three vias to reduce the parasitic inductance.
• Maintain the FB trace away from BOOT and SW traces.
• Minimize the area of switch node.
• Use a single ground. Do not use separate signal and power ground.
• Use 3 × 7 thermal vias as suggested in Land Pattern Data in 机械、封装和可订购信息.

10.2 Layout Example

The TPS56221EVM layout is shown in Figure 25 through Figure 30 for reference.

Figure 25. TPS56221EVM Top Assembly Drawing (Top view)

Figure 27. TPS56221EVM Top Copper (Top View)

Figure 29. TPS56221EVM Internal 2 (Top View)

Figure 26. TPS56221EVM Bottom Assembly Drawing (Bottom view)

Figure 28. TPS56221EVM Internal 1 (Top View)

Figure 30. TPS56221EVM Bottom Copper (Top View)